EPM570GT144C5 - 570 LEs CPLD MAX II 144TQFP | Intel
MPN: EPM570GT144C5 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $25.86 | $25.86 |
| 10 | $23.1 | $231.00 |
| 100 | $19.45 | $1,945.00 |
| 500 | $16.85 | $8,425.00 |
| 1,000 | $14.2 | $14,200.00 |
Drop-in alternatives for EPM570GT144C5 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM570GT144C4
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View Datasheet βEPM570GT144C4N
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View Datasheet βEPM570GT144C3N
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View Datasheet βEPM570GT144C3
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet βEPM570GT144C5 Maximum Ratings & Electrical Characteristics
| Series | MAX II |
| Family | MAX II G |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | 570 |
| Macrocells | 440 |
| User I/O Pins | 80 |
| User Flash Memory | 8.0 Kbits |
| Pin-to-Pin Delay (tPD) | 5.4 ns |
| Programmable Type | In-System Programmable (Flash) |
| Core Voltage VCCINT | 1.71 V to 1.89 V (internal regulator) |
| I/O Bank Voltage VCCIO | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| LVDS Support | Yes (MAX II G feature, up to 300 Mbps) |
| Operating Temperature | 0C to +85C (commercial) |
| Package | 144-TQFP (20x20 mm) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
EPM570GT144C5 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | GND β Ground |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 37 | I/O β User I/O pin (bank 2) |
| Pin 38 | I/O β User I/O pin (bank 2) |
| Pin 39 | I/O β User I/O pin (bank 2) |
| Pin 40 | I/O β User I/O pin (bank 2) |
| Pin 41 | I/O β User I/O pin (bank 2) |
| Pin 42 | I/O β User I/O pin (bank 2) |
| Pin 43 | I/O β User I/O pin (bank 2) |
| Pin 44 | I/O β User I/O pin (bank 2) |
| Pin 45 | I/O β User I/O pin (bank 2) |
| Pin 46 | I/O β User I/O pin (bank 2) |
| Pin 47 | I/O β User I/O pin (bank 2) |
| Pin 48 | I/O β User I/O pin (bank 2) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O pin (bank 2) |
| Pin 51 | I/O β User I/O pin (bank 2) |
| Pin 52 | I/O β User I/O pin (bank 2) |
| Pin 53 | I/O β User I/O pin (bank 2) |
| Pin 54 | I/O β User I/O pin (bank 2) |
| Pin 55 | I/O β User I/O pin (bank 3) |
| Pin 56 | I/O β User I/O pin (bank 3) |
| Pin 57 | I/O β User I/O pin (bank 3) |
| Pin 58 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 59 | I/O β User I/O pin (bank 3) |
| Pin 60 | I/O β User I/O pin (bank 3) |
| Pin 61 | I/O β User I/O pin (bank 3) |
| Pin 62 | I/O β User I/O pin (bank 3) |
| Pin 63 | I/O β User I/O pin (bank 3) |
| Pin 64 | I/O β User I/O pin (bank 3) |
| Pin 65 | I/O β User I/O pin (bank 3) |
| Pin 66 | I/O β User I/O pin (bank 3) |
| Pin 67 | I/O β User I/O pin (bank 3) |
| Pin 68 | I/O β User I/O pin (bank 3) |
| Pin 69 | I/O β User I/O pin (bank 3) |
| Pin 70 | I/O β User I/O pin (bank 3) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin (bank 3) |
| Pin 73 | I/O β User I/O pin (bank 3) |
| Pin 74 | I/O β User I/O pin (bank 3) |
| Pin 75 | I/O β User I/O pin (bank 3) |
| Pin 76 | I/O β User I/O pin (bank 3) |
| Pin 77 | I/O β User I/O pin (bank 3) |
| Pin 78 | I/O β User I/O pin (bank 3) |
| Pin 79 | I/O β User I/O pin (bank 3) |
| Pin 80 | I/O β User I/O pin (bank 3) |
| Pin 81 | I/O β User I/O pin (bank 3) |
| Pin 82 | I/O β User I/O pin (bank 3) |
| Pin 83 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 84 | I/O β User I/O pin (bank 3) |
| Pin 85 | I/O β User I/O pin (bank 3) |
| Pin 86 | I/O β User I/O pin (bank 3) |
| Pin 87 | I/O β User I/O pin (bank 3) |
| Pin 88 | I/O β User I/O pin (bank 3) |
| Pin 89 | I/O β User I/O pin (bank 3) |
| Pin 90 | I/O β User I/O pin (bank 3) |
| Pin 91 | TDI β JTAG Test Data In |
| Pin 92 | TCK β JTAG Test Clock |
| Pin 93 | TMS β JTAG Test Mode Select |
| Pin 94 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 95 | I/O β User I/O pin (bank 4) |
| Pin 96 | I/O β User I/O pin (bank 4) |
| Pin 97 | I/O β User I/O pin (bank 4) |
| Pin 98 | I/O β User I/O pin (bank 4) |
| Pin 99 | I/O β User I/O pin (bank 4) |
| Pin 100 | GND β Ground |
| Pin 101 | I/O β User I/O pin (bank 4) |
| Pin 102 | I/O β User I/O pin (bank 4) |
| Pin 103 | I/O β User I/O pin (bank 4) |
| Pin 104 | I/O β User I/O pin (bank 4) |
| Pin 105 | I/O β User I/O pin (bank 4) |
| Pin 106 | I/O β User I/O pin (bank 4) |
| Pin 107 | I/O β User I/O pin (bank 4) |
| Pin 108 | TDO β JTAG Test Data Out |
| Pin 109 | I/O β User I/O pin (bank 4) |
| Pin 110 | I/O β User I/O pin (bank 4) |
| Pin 111 | I/O β User I/O pin (bank 4) |
| Pin 112 | I/O β User I/O pin (bank 4) |
| Pin 113 | I/O β User I/O pin (bank 4) |
| Pin 114 | I/O β User I/O pin (bank 4) |
| Pin 115 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 116 | I/O β User I/O pin (bank 4) |
| Pin 117 | I/O β User I/O pin (bank 4) |
| Pin 118 | I/O β User I/O pin (bank 4) |
| Pin 119 | I/O β User I/O pin (bank 4) |
| Pin 120 | I/O β User I/O pin (bank 4) |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β User I/O pin (bank 4) |
| Pin 123 | I/O β User I/O pin (bank 4) |
| Pin 124 | I/O β User I/O pin (bank 4) |
| Pin 125 | I/O β User I/O pin (bank 4) |
| Pin 126 | I/O β User I/O pin (bank 4) |
| Pin 127 | I/O β User I/O pin (bank 4) |
| Pin 128 | I/O β User I/O pin (bank 4) |
| Pin 129 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 130 | I/O β User I/O pin (bank 4) |
| Pin 131 | I/O β User I/O pin (bank 4) |
| Pin 132 | I/O β User I/O pin (bank 4) |
| Pin 133 | I/O β User I/O pin (bank 1) |
| Pin 134 | I/O β User I/O pin (bank 1) |
| Pin 135 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 136 | I/O β User I/O pin (bank 1) |
| Pin 137 | I/O β User I/O pin (bank 1) |
| Pin 138 | I/O β User I/O pin (bank 1) |
| Pin 139 | GND β Ground |
| Pin 140 | I/O β User I/O pin (bank 1) |
| Pin 141 | I/O β User I/O pin (bank 1) |
| Pin 142 | I/O β User I/O pin (bank 1) |
| Pin 143 | I/O β User I/O pin (bank 1) |
| Pin 144 | I/O β User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570GT144C5 is suitable for 6 applications: Microcontroller I/O Expansion, Bus Interface Bridging, Power Supply Sequencing and Supervisory Logic, Address Decoding and Memory Interfacing, Industrial Control Logic, Communications Equipment Glue Logic.
Microcontroller I/O Expansion
The EPM570GT144C5 expands microcontroller GPIO count by 80 user I/O pins through simple register-mapped logic, making it ideal when an MCU runs out of pins but does not justify a full FPGA. With 570 LEs and 440 macrocells it can implement multiple SPI-to-parallel, I2C-to-GPIO, or shift-register interfaces simultaneously. The 5.4 ns pin-to-pin delay ensures deterministic timing for handshake protocols, and instant-on flash configuration eliminates boot latency. MultiVolt I/O banks support 1.5V/1.8V/2.5V/3.3V peripherals from a single 3.3V supply, simplifying mixed-voltage designs.
Recommended
Bus Interface Bridging
The EPM570GT144C5 bridges mismatched bus protocols such as SPI to parallel, I2C to GPIO, or UART to LVDS, providing glue logic between processors running at different voltages. Its deterministic 5.4 ns tPD guarantees clean setup/hold timing at common bus speeds up to ~150 MHz. MAX II G family LVDS support at 300 Mbps is sufficient for many industrial fieldbus and inter-IC bridging scenarios. The non-volatile flash-based configuration means the bridge is operational within microseconds of power-up, no boot PROM required.
Recommended
Power Supply Sequencing and Supervisory Logic
The EPM570GT144C5 implements power supply sequencers and supervisor logic for multi-rail systems, replacing discrete timing circuits with a single programmable device. Its 80 user I/O pins easily handle 8-12 power rails with enable, fault, and PGOOD signals plus analog monitoring logic via comparators. The deterministic 5.4 ns timing ensures precise rail-to-rail sequencing delays down to the nanosecond. Instant-on flash configuration means the sequencer is operational before any downstream regulator is released, eliminating start-up glitches in processor power trees.
Recommended
Address Decoding and Memory Interfacing
The EPM570GT144C5 provides high-speed address decoding and chip-select logic for processor-to-memory and processor-to-peripheral interfaces, replacing multiple 74-series decoders with one device. With 5.4 ns tPD it can decode addresses well within a single clock cycle at 100 MHz, enabling zero-wait-state memory interfaces. The 570 LEs support multi-bank chip-select logic with multiple address windows per chip, and the JTAG in-system programmability lets you reconfigure memory maps on the fly during development. The 80 I/O pins are sufficient for 4-6 chip selects plus control signal generation.
Recommended
Industrial Control Logic
The EPM570GT144C5 serves as the central logic engine in industrial control boards, implementing deterministic state machines, encoder counters, and PWM generation. Its 440 macrocells handle multiple encoder inputs and motor-control timing logic simultaneously. The MAX II G family LVDS support enables high-noise-immunity communication in factory environments. MultiVolt I/O banks connect directly to 3.3V MCUs and 5V-tolerant sensors through level shifting. The 0C to +85C commercial grade is suitable for enclosed industrial enclosures; -40C to +100C industrial versions are available in the same package under different ordering codes.
Recommended
Communications Equipment Glue Logic
The EPM570GT144C5 implements glue logic in networking and telecom equipment, including line-card interface logic, clock distribution steering, and protocol converters. The 5.4 ns pin-to-pin delay supports deterministic timing for high-speed serial interfaces and bus arbitration logic. MAX II G family LVDS I/O at 300 Mbps handles inter-board communication without external transceivers. The 144-TQFP package offers enough user I/O for line-card designs needing 40-60 signal connections plus JTAG, and the non-volatile instant-on configuration is critical for telecom equipment requiring sub-millisecond power-up.
Recommended
Recommended Products Summary
Engineering reference data for EPM570GT144C5 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570GT144C4 | EPM570GT144C4N | EPM570GT144C3N | EPM570GT144C3 |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 144-TQFP (20x20 mm) | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same |
| Logic Elements | 570 | 570 | 570 | 570 | 570 |
| Macrocells | 440 | 440 | 440 | 440 | 440 |
| User I/O Pins | 80 | 80 | 80 | 80 | 80 |
| Pin-to-Pin Delay (tPD) | 5.4 ns (C5) | ~7 ns (C4) | ~7 ns (C4) | ~10 ns (C3) | ~10 ns (C3) |
| User Flash Memory | 8.0 Kbits | 8.0 Kbits | 8.0 Kbits | 8.0 Kbits | 8.0 Kbits |
| Temperature Grade | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Lead-Free Finish | SnPb (standard) | SnPb | Lead-free (Pb-free) | Lead-free (Pb-free) | SnPb |
Key Differentiators
- Fastest C5 speed within MAX II G 144-TQFP family (vs EPM570GT144C4)
- SnPb lead finish availability (vs EPM570GT144C4N)
- High I/O count for the 144-TQFP package (vs EPM570GT100C5)
Design Notes
The EPM570GT144C5 requires a stable 3.3V VCCIO supply for the I/O banks and an internal 1.71V-1.89V VCCINT rail generated by an on-chip voltage regulator from VCCIO. Bypass each VCCIO pin with a 0.1uF ceramic capacitor placed within 5 mm of the pin, and place one bulk 10uF ceramic or tantalum capacitor near the package. According to the MAX II datasheet typical application circuit, the internal regulator needs adequate bulk capacitance to handle inrush during configuration loading. Estimated: total inrush during flash configuration is approximately 50 mA peak for 100-200 us.
Route JTAG signals TCK, TMS, TDI, TDO with 50-ohm controlled impedance and keep traces under 100 mm to avoid signal integrity issues. Place the JTAG header or connector within 50 mm of the device. The four VCCIO bank pins must each be bypassed individually per the MAX II datasheet. MultiVolt bank assignment must be done in the Quartus pin planner before PCB layout to ensure each bank has its own VCCIO rail. Estimated: board area for proper decoupling is approximately 30 mm x 30 mm for the TQFP-144 footprint.
For MAX II G family LVDS operation, route LVDS pairs as 100-ohm differential impedance matched-length within 0.5 mm. Maximum LVDS data rate is 300 Mbps. Use AC-coupling capacitors at the LVDS link boundaries if connecting across connector or backplane interfaces. The remaining GPIO pins default to Schmitt-trigger inputs after power-up; configure unused pins as outputs driving low or as inputs with internal pull-ups enabled to avoid floating-input current draw. Estimated: floating-input leakage per pin is approximately 10 uA.
Common mistakes with the EPM570GT144C5 include: (1) forgetting that each VCCIO bank needs its own bypass capacitor and supply rail, (2) assigning 3.3V and 1.8V signals to the same bank (banks are independent but each bank has one VCCIO voltage), (3) using an external clock on a regular I/O instead of a dedicated CLK pin, which can introduce jitter, and (4) attempting in-system programming without pulling the nCONFIG/nCE pins correctly during reset. Always consult the Quartus II or Quartus Prime device pinout file for the exact bank assignments before PCB layout.
Compliance Information
RoHS compliant per distributor listing; SnPb finish (not lead-free) is the standard C5 variant - choose N-suffix variants (e.g. EPM570GT144C5N) for lead-free Pb-free RoHS-compliant finishes. Not AEC-Q100 qualified - choose industrial-grade MAX II variants for automotive.
