EPM3128ATI144-10AA - 128-Macrocell MAX 3000A CPLD, 10ns, 144-TQFP | Intel
MPN: EPM3128ATI144-10AA ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EPM3128ATI144-10AA — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM3128ATI144-10
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View Datasheet →EPM3128ATI144-10AA Maximum Ratings & Electrical Characteristics
| Series | MAX 3000A |
| Programmable Type | In System Programmable |
| Logic Elements / Blocks | 8 LABs |
| Number of Macrocells | 128 |
| Number of Gates | 2,500 usable gates |
| User I/O Pins | 96 |
| Propagation Delay (tPD) Max | 10 ns |
| Internal fMAX | 98 MHz |
| Supply Voltage - Internal | 3.0 V to 3.6 V |
| Operating Temperature | -40 °C to +85 °C (industrial, 'I' suffix) |
| Mounting Type | Surface Mount |
| Package / Case | 144-LQFP |
| Supplier Device Package | 144-TQFP (20x20 mm) |
| Memory Type | EEPROM-based |
| JTAG / ISP Support | Yes (IEEE 1149.1) |
| MultiVolt I/O | Yes (1.5/1.8/2.5/3.3 V) |
EPM3128ATI144-10AA 144-tqfp (20x20 mm) Pin Configuration Guide
Complete pinout information for EPM3128ATI144-10AA (144-tqfp (20x20 mm) package) with 96 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM3128ATI144-10AA.
Refer to the datasheet for full pin configuration.
Estimated pin count: 96 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATI144-10AA is suitable for 6 applications: Address Decoding and Chip-Select Generation, Bus Interface Bridging (PCI / VME / ISA), Glue-Logic Consolidation in 3.3 V Systems, Synchronous State-Machine Controllers, I/O Expansion for Microcontrollers, Legacy Industrial Control and Telecom Equipment.
Address Decoding and Chip-Select Generation
The EPM3128ATI144-10AA's deterministic 10 ns pin-to-pin delay makes it ideal for generating chip-select signals from a microprocessor address bus in 3.3 V systems. With 128 macrocells and 96 user I/O pins, a single device can decode multiple peripheral banks and consolidate the discrete 74-series logic that would otherwise occupy significant PCB area. Designers can program the AND/OR array to implement up to 32 product terms per macrocell, supporting complex address-range decoding. The EEPROM-based non-volatile configuration means the device powers up active without an external boot PROM - critical for boot ROM, memory-mapped register selection, and bus-wait-state generation where deterministic timing is mandatory.
Recommended
Bus Interface Bridging (PCI / VME / ISA)
The 96 I/O pins and 10 ns tPD of the EPM3128ATI144-10AA are well matched to legacy bus-bridging applications such as PCI-to-local-bus, VME bus arbitration, and ISA-to-ISA timing translation. The 3.3 V VCCINT with MultiVolt I/O banks allows direct interface to 5 V-tolerant legacy peripherals when the I/O bank is powered at 3.3 V and external series resistors are used. Eight global clock and clear networks support synchronous bus protocols. The IEEE 1149.1 JTAG interface permits in-system programming during board bring-up and post-assembly rework without removing the part - a major advantage over socketed discrete-logic designs in telecom backplane applications.
Recommended
Glue-Logic Consolidation in 3.3 V Systems
The EPM3128ATI144-10AA is widely used to replace 5-15 discrete 74-series TTL/CMOS parts (gates, muxes, latches, flip-flops) in industrial 3.3 V designs, reducing PCB area, BOM count, and assembly cost. Its 8 LABs and 128 macrocells comfortably fit typical glue-logic patterns: address latch + chip-select decoder + interrupt arbiter + status register, all in one device. The instant-on EEPROM configuration eliminates the boot-time delay of FPGAs, making it suitable for reset-distribution and power-good sequencing where the system must respond within microseconds of rail ramp. The industrial -40 °C to +85 °C temperature grade supports factory-floor and outdoor enclosures.
Recommended
Synchronous State-Machine Controllers
The deterministic 10 ns tPD and 98 MHz fMAX of the EPM3128ATI144-10AA support synchronous state machines operating up to ~50 MHz system clock (allowing two tPD per state). Each macrocell contains a flip-flop with programmable clear, clock-enable, and preset - the building blocks of Moore and Mealy machines. The 128 macrocells can implement several medium-complexity state machines concurrently, such as motor-control sequencers, UART-style serializers, or protocol converters. MultiVolt I/O allows the CPLD to drive 1.8 V or 2.5 V ASICs directly while running from a 3.3 V core supply, simplifying mixed-voltage designs.
Recommended
I/O Expansion for Microcontrollers
When an 8-bit or 32-bit microcontroller runs out of GPIO pins, the EPM3128ATI144-10AA can provide 96 additional I/O lines controlled via SPI, I2C, or parallel interface from the MCU. The 10 ns propagation delay enables real-time response for keypad scanning, LED multiplexing, or LCD segment driving. The 144-TQFP package provides ample I/O for human-interface front panels. In-system programmability allows last-minute pin-assignment changes without board rework - simply regenerate the JEDEC file and re-program via JTAG during development.
Recommended
Legacy Industrial Control and Telecom Equipment
The EPM3128ATI144-10AA's industrial -40 °C to +85 °C temperature range and mature MAX 3000A architecture make it a long-life choice for legacy industrial-control PLCs, telecom line cards, and military/aerospace systems that must remain in production for 10-20 years. The EEPROM configuration retains the design through power cycles without a separate boot PROM, reducing board failure modes. The deterministic tPD is preferred in safety-critical interlocks where designers must guarantee worst-case response time without statistical timing analysis. Verified distributor stock at Heisener (2,832 pieces) and Kynix supports ongoing maintenance and spare-parts requirements.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATI144-10AA — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATI144-10 | EPM3128ATC144-10N | EPM3128ATC144-7N | EPM3128ATC144-5N | EPM3128ATC144-10 |
|---|---|---|---|---|---|---|
| Package | 144-TQFP (20x20 mm) | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| tPD (max) | 10 ns | 10 ns | 10 ns | 7.5 ns | 5 ns | 10 ns |
| Temperature Grade | Industrial -40C to +85C | Industrial -40C to +85C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C |
| User I/O | 96 | 96 | 96 | 96 | 96 | 96 |
| Core Voltage | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Family / Architecture | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A |
| fMAX | 98 MHz | 98 MHz | 98 MHz | [DATA_NEEDED] | [DATA_NEEDED] | 98 MHz |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade in the same 144-TQFP footprint (vs EPM3128ATC144-10N)
- Faster 5 ns and 7.5 ns variants available in the same footprint (vs EPM3128ATC144-5N and EPM3128ATC144-7N)
- Same-package migration path to MAX II for new designs (vs EPM1270T144C5N)
- Non-volatile EEPROM configuration = instant-on, no boot PROM (vs SRAM-based FPGAs (e.g. Cyclone series))
Design Notes
The EPM3128ATI144-10AA requires both core (VCCINT 3.0-3.6 V) and I/O bank (VCCIO) supplies. Decouple each VCC pin with a 0.1 µF ceramic capacitor placed within 5 mm of the package, plus a bulk 10-100 µF tantalum or polymer capacitor at the board power entry. Estimated ICC (active) for a fully utilized 128-macrocell design is approximately 50-100 mA at 3.3 V - budget 0.3-0.5 W for the device alone. MultiVolt I/O banks can each be powered at 1.5/1.8/2.5/3.3 V independently, but unused banks should still be tied to a valid VCCIO rail (not left floating) to prevent I/O buffer oscillation.
The 144-TQFP package has 0.5 mm pitch leads - use a PCB land pattern with 0.30 mm wide pads and a 0.50 mm pitch per IPC-7351 nominal. Enable a continuous ground plane on the layer beneath the CPLD for return-path integrity, especially around JTAG signals. Route TCK, TMS, TDI, TDO as a bus with similar lengths (within 25 mm) to preserve JTAG signal integrity; add 10 kΩ pull-ups on TMS and TDI per IEEE 1149.1. Place the JTAG header within 50 mm of the TQFP to keep programming cables short.
Do not confuse the EPM3128A (MAX 3000A family, 3.3 V core) with the legacy EPM3128 (MAX 3000 family, 5 V core) - they are not pin-compatible. When migrating a design from industrial 'I' to commercial 'C' temperature grade, verify that the operating environment stays within 0-70 °C including self-heating. Do not leave JTAG pins floating - TCK must be pulled to a defined logic level (idle-low per JTAG convention). The MAX 3000A family is obsolete as of 2026; for new designs, evaluate MAX II (EPM240T100, EPM1270T144) or MAX V (5M570ZT100) which offer lower power, more logic, and modern Quartus support in compatible footprints.
Compliance Information
RoHS compliant per Intel/Altera product declaration; 'AA' suffix indicates NiPdAu lead-free finish. Industrial temperature grade (-40C to +85C) per 'I' suffix. Halogen-free status not explicitly stated in available distributor data - set to unknown. AEC-Q100 not applicable (CPLD is not an automotive-qualified part).
