EPM7256AETI144-7 - 256-Macro MAX 7000A CPLD, TQFP-144 | Intel
MPN: EPM7256AETI144-7 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $88.44 | $88.44 |
| 10 | $79.6 | $796.00 |
| 100 | $70.92 | $7,092.00 |
| 500 | $62.23 | $31,115.00 |
| 1,000 | $53.55 | $53,550.00 |
Drop-in alternatives for EPM7256AETI144-7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7256AETI144-7N
✅ Drop-In✓ In Stock
$29.81 / Unit
View Datasheet →EPM7256AETC144-7N
✅ Drop-In✓ In Stock
$29.75 / Unit
View Datasheet →EPM7256AETI144-10N
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EPM7256AETC144-10N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$15.95 / Unit
View Datasheet →EPM7256AETC144-10
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$31.4 / Unit
View Datasheet →EPM7256AETC144-5N
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPM7256AETI144-7 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 |
| Usable Gates | 5,000 |
| User I/Os | 36 |
| Logic Array Blocks (LABs) | 16 |
| Pin-to-Pin Delay (tPD) | 7 ns |
| Maximum Frequency (fMAX) | 126.6 MHz |
| Supply Voltage (Core) | 3.3 V |
| I/O Standard Support | MultiVolt (2.5 V / 3.3 V / 5 V) |
| Programming Interface | IEEE 1149.1 (JTAG) / ByteBlaster |
| Package | TQFP-144 (20x20 mm, 0.5 mm pitch) |
| Operating Temperature | -40C to +85C (Industrial) |
| Configuration Memory | Non-volatile EEPROM (instant-on, no boot PROM) |
| Mounting Type | Surface Mount |
EPM7256AETI144-7 Pin Configuration
| Pin 1 | I/O — User I/O pin |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | I/O — User I/O pin |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | GND — Ground |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | GND — Ground |
| Pin 28 | VCCINT — 3.3 V core supply |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | GCLK1 — Global clock input 1 |
| Pin 39 | OE2/GCLK3 — Global OE or global clock 3 |
| Pin 40 | OE1 — Global output enable 1 |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | GND — Ground |
| Pin 54 | VCCIO — I/O supply (2.5 V/3.3 V/5 V) |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | GCLK2 — Global clock input 2 |
| Pin 68 | OE4 — Global output enable 4 |
| Pin 69 | OE3 — Global output enable 3 |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | GND — Ground |
| Pin 82 | VCCIO — I/O supply (2.5 V/3.3 V/5 V) |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | I/O — User I/O pin |
| Pin 87 | I/O — User I/O pin |
| Pin 88 | I/O — User I/O pin |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | I/O — User I/O pin |
| Pin 91 | I/O — User I/O pin |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | I/O — User I/O pin |
| Pin 97 | I/O — User I/O pin |
| Pin 98 | TDI — JTAG Test Data In |
| Pin 99 | TMS — JTAG Test Mode Select |
| Pin 100 | TCK — JTAG Test Clock |
| Pin 101 | VCCINT — 3.3 V core supply |
| Pin 102 | GND — Ground |
| Pin 103 | TDO — JTAG Test Data Out |
| Pin 104 | I/O — User I/O pin |
| Pin 105 | I/O — User I/O pin |
| Pin 106 | I/O — User I/O pin |
| Pin 107 | GND — Ground |
| Pin 108 | VCCIO — I/O supply (2.5 V/3.3 V/5 V) |
| Pin 109 | I/O — User I/O pin |
| Pin 110 | I/O — User I/O pin |
| Pin 111 | I/O — User I/O pin |
| Pin 112 | I/O — User I/O pin |
| Pin 113 | I/O — User I/O pin |
| Pin 114 | I/O — User I/O pin |
| Pin 115 | I/O — User I/O pin |
| Pin 116 | I/O — User I/O pin |
| Pin 117 | I/O — User I/O pin |
| Pin 118 | I/O — User I/O pin |
| Pin 119 | I/O — User I/O pin |
| Pin 120 | I/O — User I/O pin |
| Pin 121 | I/O — User I/O pin |
| Pin 122 | I/O — User I/O pin |
| Pin 123 | I/O — User I/O pin |
| Pin 124 | I/O — User I/O pin |
| Pin 125 | I/O — User I/O pin |
| Pin 126 | I/O — User I/O pin |
| Pin 127 | I/O — User I/O pin |
| Pin 128 | I/O — User I/O pin |
| Pin 129 | I/O — User I/O pin |
| Pin 130 | I/O — User I/O pin |
| Pin 131 | I/O — User I/O pin |
| Pin 132 | GND — Ground |
| Pin 133 | VCCIO — I/O supply (2.5 V/3.3 V/5 V) |
| Pin 134 | I/O — User I/O pin |
| Pin 135 | I/O — User I/O pin |
| Pin 136 | I/O — User I/O pin |
| Pin 137 | I/O — User I/O pin |
| Pin 138 | I/O — User I/O pin |
| Pin 139 | I/O — User I/O pin |
| Pin 140 | I/O — User I/O pin |
| Pin 141 | I/O — User I/O pin |
| Pin 142 | I/O — User I/O pin |
| Pin 143 | I/O — User I/O pin |
| Pin 144 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7256AETI144-7 is suitable for 6 applications: Industrial Control Glue Logic, Bus Interface Bridging, Motor Control State Machines, Legacy Peripheral Bridging, Power-Up Sequencing and Supervisor Logic, Brown-Out-Tolerant Embedded Controllers.
Industrial Control Glue Logic
The EPM7256AETI144-7 fits industrial control glue logic because of its non-volatile instant-on configuration, industrial -40C to +85C temperature grade and deterministic 7 ns pin-to-pin delay. With 256 macrocells and 36 user I/Os it can replace 4-6 discrete 22V10/ GAL devices on a PLC backplane, replacing address decoding, interrupt steering, watchdog timing and bus arbitration in one chip. Unlike SRAM-based FPGAs it requires no boot PROM and therefore survives brown-outs and cold starts without reconfiguration - a critical requirement on factory floors with unstable 24 V supplies.
Recommended
Bus Interface Bridging
The EPM7256AETI144-7 is well suited to bus-bridge applications such as ISA-to-PCI, parallel-to-LVDS or 8-bit microcontroller to 16-bit/32-bit peripheral translation. Its MultiVolt I/O allows the CPLD to interface 5 V peripherals and 3.3 V processors on the same board without external level shifters, and the 256 macrocells provide enough logic for handshaking, byte-swapping and wait-state insertion. The 7 ns tPD supports synchronous bus cycles up to 126.6 MHz, while JTAG programming lets manufacturers re-spin bus widths in production without reworking the PCB.
Recommended
Motor Control State Machines
The EPM7256AETI144-7 is a strong fit for motor-drive state machines because its deterministic 7 ns combinational delay and 126.6 MHz fMAX give predictable PWM generation, commutation timing and fault-interval response. Industrial temperature grade lets it sit next to IGBT gate drivers on the same PCB, and 36 user I/Os are enough to handle Hall-sensor inputs, encoder feedback and six PWM channels for a 3-phase inverter. Non-volatile EEPROM configuration means the controller powers up in a known safe state, preventing shoot-through on cold start.
Recommended
Legacy Peripheral Bridging
Legacy peripherals such as 5 V SRAM, 8-bit parallel ADCs and ISA-bus cards can be bridged to modern 3.3 V MCUs using the EPM7256AETI144-7 with its MultiVolt I/O. The 5 V-tolerant I/O banks connect directly to legacy 5 V devices while the 3.3 V core and 3.3 V I/O connect to the host processor, eliminating discrete level shifters. 256 macrocells accommodate address-latch, chip-select decoder, bus-direction control and timing-glue logic in a single chip, and JTAG boundary-scan (IEEE 1149.1) aids in-circuit test of the bridge.
Recommended
Power-Up Sequencing and Supervisor Logic
The EPM7256AETI144-7 excels at power-sequencing tasks because its EEPROM-based non-volatile configuration is available the instant VCCINT crosses its threshold - no boot PROM, no configuration delay. A 3-rail board can use a single CPLD to enforce power-up order (core before I/O before analog), monitor PG (power-good) inputs, and assert RESET to downstream processors with millisecond timing. Industrial temp grade and 5 V-tolerant I/O let it monitor 24 V industrial rails, and JTAG allows late-stage firmware adjustments without board rework.
Recommended
Brown-Out-Tolerant Embedded Controllers
The EPM7256AETI144-7 is a strong fit for brown-out-tolerant embedded controllers because its non-volatile EEPROM configuration retains the logic design across full power loss - no reconfiguration, no boot wait, no spurious outputs on cold start. Combined with its 3.3 V core and 5 V-tolerant I/O, the part can ride through noisy 24 V industrial supplies while keeping deterministic timing for protective interlocks. The 256-macrocell capacity is sufficient for state machines, watchdog timers, fault logging and isolated communication bridges used in remote or battery-backed equipment.
Recommended
Recommended Products Summary
Engineering reference data for EPM7256AETI144-7 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7256AETI144-7N | EPM7256AETC144-7N | EPM7256AETI144-10N | EPM7256AETC144-10N | EPM7256AETC144-5N |
|---|---|---|---|---|---|---|
| Package | TQFP-144 (0.5 mm pitch, 20x20 mm) | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same |
| Brand | Intel (formerly Altera) | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Macrocells | 256 | 256 | 256 | 256 | 256 | 256 |
| Pin-to-Pin Delay (tPD) | 7 ns | 7 ns | 7 ns | 10 ns | 10 ns | 5 ns |
| Max Frequency (fMAX) | 126.6 MHz | 126.6 MHz | 126.6 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Lead-Free / RoHS | SnPb (non-RoHS) | Yes (RoHS) | Yes (RoHS) | Yes (RoHS) | Yes (RoHS) | Yes (RoHS) |
| User I/Os | 36 | 36 | 36 | 36 | 36 | 36 |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Same-footprint lead-free reflow-ready variant (vs EPM7256AETI144-7N)
- Faster 5 ns pin-to-pin delay (vs EPM7256AETC144-5N)
- Higher density alternative (vs EPM7256BTC100-7)
Design Notes
The EPM7256AETI144-7 requires a 3.3 V +/- 5% supply on VCCINT (pins 28 and 101) plus a separately decoupled VCCIO rail that can be 2.5 V, 3.3 V or 5 V depending on the logic family being interfaced. Place a 0.1 uF decoupling capacitor within 5 mm of every VCCINT and VCCIO pin, and a bulk 10 uF tantalum near the package to handle inrush during in-system programming (ISP). Power-up ramp should be monotonic between 0 V and 3.3 V in at least 1 ms for reliable configuration. Estimated Icc at 3.3 V is 30-60 mA in static operation and can rise to ~200 mA during simultaneous switching of all 36 I/Os.
The TQFP-144 package has a 0.5 mm pin pitch and requires fine-pitch PCB design rules: 0.15 mm trace width, 0.15 mm trace spacing and 0.4 mm via diameter. Tie all GND pins (13, 27, 53, 81, 102, 107, 132) to a solid ground plane on the top layer to provide low-impedance return paths for the 36 I/Os. Use 5 mil solder paste on land pads to avoid bridging, and reflow within the JEDEC J-STD-020 profile matching the part finish (SnPb for -7, lead-free for -7N).
Avoid these EPM7256AETI144-7 pitfalls: (1) Do not mix 5 V and 3.3 V on the same VCCIO bank - all I/Os in a bank share one VCCIO and cannot tolerate mixed voltages. (2) Do not apply input signals until VCCINT reaches 3.0 V or 5 V-tolerant I/Os can latch up. (3) JTAG chain length should not exceed 8 devices or the TCK rise time will degrade below 10 ns - insert a JTAG buffer for longer chains. (4) Unused I/O pins must be set to 'output enable off' in the Quartus / MAX+PLUS II pin assignments, otherwise they float and consume power. (5) Do not hot-plug the device when VCCIO is unpowered - the I/Os must be powered before signals are applied.
Compliance Information
RoHS: non_compliant per part suffix -7 (SnPb finish). Choose -7N for lead-free RoHS reflow compliance. REACH compliant per Altera/Intel product declaration. AEC-Q100 not applicable - this is a commercial/industrial CPLD, not automotive-qualified.
