EPM7256BQC208-7 - 256-Macro MAX 7000B CPLD, 208-PQFP | Intel
MPN: EPM7256BQC208-7 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EPM7256BQC208-7 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7256BQC208-10
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7256BQI208-7
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7256AQC208-7
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$27.2 / Unit
View Datasheet βEPM7256AQI208-10
β Drop-Inβ In Stock
$13.22 / Unit
View Datasheet βEPM7256BQC208-7 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000B |
| Device Type | CPLD - Complex Programmable Logic Device |
| Usable Gates | 5,000 |
| Macro Cells | 256 |
| User I/Os | 164 |
| Logic Elements / LABs | 16 Logic Array Blocks |
| Maximum Internal Frequency | 126.6 MHz |
| Propagation Delay (tPD) | 7.5 ns (-7 speed grade) |
| Core Supply Voltage | 2.5 V |
| Operating Temperature | 0C to +90C (commercial) |
| Package | 208-pin PQFP |
| Mounting Type | Surface Mount |
| Configuration Memory | Non-volatile EEPROM |
| JTAG / Boundary Scan | IEEE 1149.1 compliant |
| In-System Programmability | Yes (via JTAG) |
| RoHS Status | Compliant per distributor listings |
EPM7256BQC208-7 Pin Configuration
| Pin 1 | GND β Ground |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | VCCINT β Core supply voltage, 2.5 V |
| Pin 7 | I/O β User I/O pin (bank 2) |
| Pin 8 | I/O β User I/O pin (bank 2) |
| Pin 9 | I/O β User I/O pin (bank 2) |
| Pin 10 | I/O β User I/O pin (bank 2) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (bank 2) |
| Pin 13 | I/O β User I/O pin (bank 2) |
| Pin 14 | I/O β User I/O pin (bank 2) |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | VCCIO1 β I/O bank 1 reference voltage |
| Pin 17 | TDI β JTAG Test Data In |
| Pin 18 | TMS β JTAG Test Mode Select |
| Pin 19 | TCK β JTAG Test Clock |
| Pin 20 | GND β Ground |
| Pin 21 | I/O β User I/O pin (bank 1) |
| Pin 22 | I/O β User I/O pin (bank 1) |
| Pin 23 | I/O β User I/O pin (bank 1) |
| Pin 24 | I/O β User I/O pin (bank 1) |
| Pin 25 | VCCINT β Core supply voltage, 2.5 V |
| Pin 26 | I/O β User I/O pin (bank 3) |
| Pin 27 | I/O β User I/O pin (bank 3) |
| Pin 28 | I/O β User I/O pin (bank 3) |
| Pin 29 | I/O β User I/O pin (bank 3) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin (bank 3) |
| Pin 32 | I/O β User I/O pin (bank 3) |
| Pin 33 | I/O β User I/O pin (bank 3) |
| Pin 34 | I/O β User I/O pin (bank 3) |
| Pin 35 | VCCIO3 β I/O bank 3 reference voltage |
| Pin 36 | I/O β User I/O pin (bank 4) |
| Pin 37 | I/O β User I/O pin (bank 4) |
| Pin 38 | I/O β User I/O pin (bank 4) |
| Pin 39 | I/O β User I/O pin (bank 4) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β User I/O pin (bank 4) |
| Pin 42 | I/O β User I/O pin (bank 4) |
| Pin 43 | I/O β User I/O pin (bank 4) |
| Pin 44 | I/O β User I/O pin (bank 4) |
| Pin 45 | VCCINT β Core supply voltage, 2.5 V |
| Pin 46 | I/O β User I/O pin (bank 2) |
| Pin 47 | I/O β User I/O pin (bank 2) |
| Pin 48 | I/O β User I/O pin (bank 2) |
| Pin 49 | I/O β User I/O pin (bank 2) |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β User I/O pin (bank 2) |
| Pin 52 | I/O β User I/O pin (bank 2) |
| Pin 53 | I/O β User I/O pin (bank 2) |
| Pin 54 | I/O β User I/O pin (bank 2) |
| Pin 55 | VCCIO2 β I/O bank 2 reference voltage |
| Pin 56 | I/O β User I/O pin (bank 1) |
| Pin 57 | I/O β User I/O pin (bank 1) |
| Pin 58 | I/O β User I/O pin (bank 1) |
| Pin 59 | I/O β User I/O pin (bank 1) |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β User I/O pin (bank 1) |
| Pin 62 | I/O β User I/O pin (bank 1) |
| Pin 63 | I/O β User I/O pin (bank 1) |
| Pin 64 | I/O β User I/O pin (bank 1) |
| Pin 65 | VCCINT β Core supply voltage, 2.5 V |
| Pin 66 | I/O β User I/O pin (bank 3) |
| Pin 67 | I/O β User I/O pin (bank 3) |
| Pin 68 | I/O β User I/O pin (bank 3) |
| Pin 69 | I/O β User I/O pin (bank 3) |
| Pin 70 | GND β Ground |
| Pin 71 | I/O β User I/O pin (bank 3) |
| Pin 72 | I/O β User I/O pin (bank 3) |
| Pin 73 | I/O β User I/O pin (bank 3) |
| Pin 74 | I/O β User I/O pin (bank 3) |
| Pin 75 | VCCIO4 β I/O bank 4 reference voltage |
| Pin 76 | I/O β User I/O pin (bank 4) |
| Pin 77 | I/O β User I/O pin (bank 4) |
| Pin 78 | I/O β User I/O pin (bank 4) |
| Pin 79 | I/O β User I/O pin (bank 4) |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β User I/O pin (bank 4) |
| Pin 82 | I/O β User I/O pin (bank 4) |
| Pin 83 | I/O β User I/O pin (bank 4) |
| Pin 84 | I/O β User I/O pin (bank 4) |
| Pin 85 | VCCINT β Core supply voltage, 2.5 V |
| Pin 86 | I/O β User I/O pin (bank 2) |
| Pin 87 | I/O β User I/O pin (bank 2) |
| Pin 88 | I/O β User I/O pin (bank 2) |
| Pin 89 | I/O β User I/O pin (bank 2) |
| Pin 90 | GND β Ground |
| Pin 91 | I/O β User I/O pin (bank 2) |
| Pin 92 | I/O β User I/O pin (bank 2) |
| Pin 93 | I/O β User I/O pin (bank 2) |
| Pin 94 | I/O β User I/O pin (bank 2) |
| Pin 95 | VCCIO2 β I/O bank 2 reference voltage |
| Pin 96 | I/O β User I/O pin (bank 1) |
| Pin 97 | I/O β User I/O pin (bank 1) |
| Pin 98 | I/O β User I/O pin (bank 1) |
| Pin 99 | I/O β User I/O pin (bank 1) |
| Pin 100 | GND β Ground |
| Pin 101 | I/O β User I/O pin (bank 1) |
| Pin 102 | I/O β User I/O pin (bank 1) |
| Pin 103 | I/O β User I/O pin (bank 1) |
| Pin 104 | I/O β User I/O pin (bank 1) |
| Pin 105 | VCCINT β Core supply voltage, 2.5 V |
| Pin 106 | I/O β User I/O pin (bank 3) |
| Pin 107 | I/O β User I/O pin (bank 3) |
| Pin 108 | I/O β User I/O pin (bank 3) |
| Pin 109 | I/O β User I/O pin (bank 3) |
| Pin 110 | GND β Ground |
| Pin 111 | I/O β User I/O pin (bank 3) |
| Pin 112 | I/O β User I/O pin (bank 3) |
| Pin 113 | I/O β User I/O pin (bank 3) |
| Pin 114 | I/O β User I/O pin (bank 3) |
| Pin 115 | VCCIO3 β I/O bank 3 reference voltage |
| Pin 116 | I/O β User I/O pin (bank 4) |
| Pin 117 | I/O β User I/O pin (bank 4) |
| Pin 118 | I/O β User I/O pin (bank 4) |
| Pin 119 | I/O β User I/O pin (bank 4) |
| Pin 120 | GND β Ground |
| Pin 121 | I/O β User I/O pin (bank 4) |
| Pin 122 | I/O β User I/O pin (bank 4) |
| Pin 123 | I/O β User I/O pin (bank 4) |
| Pin 124 | I/O β User I/O pin (bank 4) |
| Pin 125 | VCCINT β Core supply voltage, 2.5 V |
| Pin 126 | I/O β User I/O pin (bank 2) |
| Pin 127 | I/O β User I/O pin (bank 2) |
| Pin 128 | I/O β User I/O pin (bank 2) |
| Pin 129 | I/O β User I/O pin (bank 2) |
| Pin 130 | GND β Ground |
| Pin 131 | I/O β User I/O pin (bank 2) |
| Pin 132 | I/O β User I/O pin (bank 2) |
| Pin 133 | I/O β User I/O pin (bank 2) |
| Pin 134 | I/O β User I/O pin (bank 2) |
| Pin 135 | VCCIO2 β I/O bank 2 reference voltage |
| Pin 136 | I/O β User I/O pin (bank 1) |
| Pin 137 | I/O β User I/O pin (bank 1) |
| Pin 138 | I/O β User I/O pin (bank 1) |
| Pin 139 | I/O β User I/O pin (bank 1) |
| Pin 140 | GND β Ground |
| Pin 141 | I/O β User I/O pin (bank 1) |
| Pin 142 | I/O β User I/O pin (bank 1) |
| Pin 143 | I/O β User I/O pin (bank 1) |
| Pin 144 | I/O β User I/O pin (bank 1) |
| Pin 145 | VCCINT β Core supply voltage, 2.5 V |
| Pin 146 | I/O β User I/O pin (bank 3) |
| Pin 147 | I/O β User I/O pin (bank 3) |
| Pin 148 | I/O β User I/O pin (bank 3) |
| Pin 149 | I/O β User I/O pin (bank 3) |
| Pin 150 | GND β Ground |
| Pin 151 | I/O β User I/O pin (bank 3) |
| Pin 152 | I/O β User I/O pin (bank 3) |
| Pin 153 | I/O β User I/O pin (bank 3) |
| Pin 154 | I/O β User I/O pin (bank 3) |
| Pin 155 | VCCIO3 β I/O bank 3 reference voltage |
| Pin 156 | I/O β User I/O pin (bank 4) |
| Pin 157 | I/O β User I/O pin (bank 4) |
| Pin 158 | I/O β User I/O pin (bank 4) |
| Pin 159 | I/O β User I/O pin (bank 4) |
| Pin 160 | GND β Ground |
| Pin 161 | I/O β User I/O pin (bank 4) |
| Pin 162 | I/O β User I/O pin (bank 4) |
| Pin 163 | I/O β User I/O pin (bank 4) |
| Pin 164 | I/O β User I/O pin (bank 4) |
| Pin 165 | VCCINT β Core supply voltage, 2.5 V |
| Pin 166 | I/O β User I/O pin (bank 2) |
| Pin 167 | I/O β User I/O pin (bank 2) |
| Pin 168 | I/O β User I/O pin (bank 2) |
| Pin 169 | I/O β User I/O pin (bank 2) |
| Pin 170 | GND β Ground |
| Pin 171 | I/O β User I/O pin (bank 2) |
| Pin 172 | I/O β User I/O pin (bank 2) |
| Pin 173 | I/O β User I/O pin (bank 2) |
| Pin 174 | I/O β User I/O pin (bank 2) |
| Pin 175 | VCCIO2 β I/O bank 2 reference voltage |
| Pin 176 | I/O β User I/O pin (bank 1) |
| Pin 177 | I/O β User I/O pin (bank 1) |
| Pin 178 | I/O β User I/O pin (bank 1) |
| Pin 179 | I/O β User I/O pin (bank 1) |
| Pin 180 | GND β Ground |
| Pin 181 | I/O β User I/O pin (bank 1) |
| Pin 182 | I/O β User I/O pin (bank 1) |
| Pin 183 | I/O β User I/O pin (bank 1) |
| Pin 184 | I/O β User I/O pin (bank 1) |
| Pin 185 | VCCINT β Core supply voltage, 2.5 V |
| Pin 186 | I/O β User I/O pin (bank 3) |
| Pin 187 | I/O β User I/O pin (bank 3) |
| Pin 188 | I/O β User I/O pin (bank 3) |
| Pin 189 | I/O β User I/O pin (bank 3) |
| Pin 190 | GND β Ground |
| Pin 191 | I/O β User I/O pin (bank 3) |
| Pin 192 | I/O β User I/O pin (bank 3) |
| Pin 193 | I/O β User I/O pin (bank 3) |
| Pin 194 | I/O β User I/O pin (bank 3) |
| Pin 195 | VCCIO3 β I/O bank 3 reference voltage |
| Pin 196 | I/O β User I/O pin (bank 4) |
| Pin 197 | I/O β User I/O pin (bank 4) |
| Pin 198 | I/O β User I/O pin (bank 4) |
| Pin 199 | I/O β User I/O pin (bank 4) |
| Pin 200 | GND β Ground |
| Pin 201 | I/O β User I/O pin (bank 4) |
| Pin 202 | I/O β User I/O pin (bank 4) |
| Pin 203 | I/O β User I/O pin (bank 4) |
| Pin 204 | I/O β User I/O pin (bank 4) |
| Pin 205 | VCCINT β Core supply voltage, 2.5 V |
| Pin 206 | TDO β JTAG Test Data Out |
| Pin 207 | DEV_CLRn β Device clear (active low) |
| Pin 208 | DEV_OE β Device output enable |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7256BQC208-7 is suitable for 6 applications: Industrial Control Glue Logic, Telecom Line-Card Interface, ASIC and FPGA Prototyping, Legacy Peripheral Glue Logic, Automotive Infotainment Bus Bridge, Test and Measurement Instrumentation.
Industrial Control Glue Logic
The EPM7256BQC208-7 is widely used in industrial PLCs and motor-control boards where 164 user I/Os and deterministic 7.5 ns tPD propagation delay let designers replace dozens of 74-series glue-logic chips with one programmable device. The non-volatile EEPROM configuration retains state through brown-outs and power cycling, which is critical for industrial equipment that must resume operation without re-flashing. The 2.5 V core with 5 V-tolerant I/O banks (via VCCIO) allows direct interfacing with legacy 5 V peripherals, optocouplers, and 24 V industrial sensors. Engineers value the JTAG in-system programmability for firmware updates on deployed equipment.
Recommended
Telecom Line-Card Interface
Telecom line cards frequently use the EPM7256BQC208-7 to perform bus arbitration, address decoding, and protocol translation between network processors and TDM/Ethernet framer ASICs. The 126.6 MHz internal frequency supports high-speed glue functions between Fast Ethernet PHYs, T1/E1 framers, and backplane buses. The deterministic timing of CPLD logic (versus FPGA soft cores) simplifies timing closure for telecom applications where jitter budgets are tight. The 208-pin PQFP package is large enough to break out 164 I/Os into multiple parallel data buses without requiring additional bus transceivers.
Recommended
ASIC and FPGA Prototyping
Designers prototyping ASICs or validating FPGA-based designs use the EPM7256BQC208-7 as a hardware emulator for glue logic that will eventually be absorbed into an ASIC. The 256 macro cells and 5,000 usable gates are sufficient to model medium-complexity state machines, FIFO controllers, and custom bus protocols. The non-volatile EEPROM lets prototype boards boot immediately without external boot PROMs, accelerating bring-up and bench testing. Quartus II design entry with schematic capture and Verilog/VHDL synthesis reduces design iteration time versus discrete TTL prototypes.
Recommended
Legacy Peripheral Glue Logic
The EPM7256BQC208-7 replaces 74HC/74FCT glue logic around microprocessors, DSPs, and memory interfaces. Typical uses include address decoding, chip-select generation, wait-state insertion, and interrupt prioritization. The 164 I/Os accommodate parallel SRAM, NOR flash, and peripheral interfaces simultaneously, eliminating the need for separate address-latch and decoder chips. Programmable pin assignments simplify PCB routing when designers need to swap signals between board revisions without re-spinning the layout.
Recommended
Automotive Infotainment Bus Bridge
In automotive infotainment systems the EPM7256BQC208-7 bridges between I2S audio buses, SPI peripherals, and CAN/LIN network segments. The MAX 7000B architecture supports 5 V-tolerant I/O banks for direct connection to legacy automotive microcontrollers and CAN transceivers. The 7.5 ns tPD keeps audio sample-rate jitter well below audible thresholds. Designers value the JTAG interface for end-of-line programming in automotive manufacturing.
Recommended
Test and Measurement Instrumentation
Test equipment such as logic analyzers, oscilloscope front-ends, and protocol exercisers use the EPM7256BQC208-7 to perform pattern generation, channel multiplexing, and trigger logic. The deterministic 7.5 ns propagation delay supports precise timing-critical trigger generation, while the 164 I/Os allow parallel pattern output across 32+ channels with margin for address and control signals. The PQFP package is large enough to expose all I/Os on a daughter-card for ribbon-cable connection to a backplane test fixture.
Recommended
Recommended Products Summary
Engineering reference data for EPM7256BQC208-7 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7256BQC208-10 | EPM7256BQI208-7 | EPM7256AQC208-7 | EPM7256AQI208-10 |
|---|---|---|---|---|---|
| Package | PQFP-208 | PQFP-208 - same | PQFP-208 - same | PQFP-208 - same | PQFP-208 - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Family | MAX 7000B | MAX 7000B | MAX 7000B | MAX 7000A | MAX 7000A |
| Macro Cells | 256 | 256 | 256 | 256 | 256 |
| Propagation Delay (tPD) | 7.5 ns (-7) | 10 ns (-10) | 7.5 ns (-7) | 7.5 ns (-7) | 10 ns (-10) |
| Core Voltage | 2.5 V | 2.5 V | 2.5 V | 3.3 V | 3.3 V |
| Operating Temperature | 0C to +90C (commercial) | 0C to +90C | -40C to +85C (industrial) | 0C to +90C | -40C to +85C (industrial) |
| User I/Os | 164 | 164 | 164 | 164 | 164 |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Same PQFP-208 package and 256 macro cells as MAX 7000A, but on a 2.5 V core (vs EPM7256AQC208-7)
- Industrial temperature option in the same PQFP-208 footprint (vs EPM7256BQI208-7)
- Same die as EPM7256BQC208-10 with -7 speed grade for 25% faster tPD (vs EPM7256BQC208-10)
Design Notes
Estimated: at typical 50 MHz toggle activity across 100 of 164 I/Os with 5 V VCCIO, dynamic current is approximately 50-80 mA from VCCIO plus 30-50 mA from VCCINT (2.5 V). Decouple each VCCINT pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, and add a 10 uF bulk capacitor per supply rail near the package. PQFP packages do not have an exposed thermal pad; use a ground pour under the device to spread heat and lower loop inductance on switching outputs.
Route JTAG signals (TDI, TDO, TMS, TCK) in a daisy-chain topology with 10K pull-ups on TMS and TCK per IEEE 1149.1. Keep JTAG traces short (<= 50 mm) and guarded by GND to avoid noise-induced programming failures. Place a 4.7K pull-up on DEV_CLRn and DEV_OE to default the device to user mode after configuration, or pull DEV_OE low to tri-state all I/Os during in-system programming.
Do not confuse the EPM7256BQC208-7 (MAX 7000B, 2.5 V core) with the EPM7256AQC208-7 (MAX 7000A, 3.3 V core). They share the same PQFP-208 footprint but require different VCCINT rails; substituting one for the other without re-routing power will damage the device. Also note that Quartus II versions earlier than 13.0 SP1 may not support the latest MAX 7000B programming algorithms - use Quartus II 13.0 SP1 or later for reliable programming file generation.
PQFP-208 leads have approximately 1.5 nH of lead inductance each, which can cause ringing on high-speed outputs above 50 MHz. For clock-like signals above 50 MHz, source-terminate with a 33-ohm series resistor to dampen reflections, and keep trace stubs < 5 mm. Place a 50-ohm characteristic-impedance reference for controlled-impedance signals routed off-device.
Compliance Information
RoHS and REACH compliance per distributor listings (DigiKey, Mouser, Arrow). The MAX 7000B family is not AEC-Q100 qualified; for automotive applications consider MAX II or MAX V automotive-grade variants.
