LMK00804BQWRGTRQ1 - 1:4 LVCMOS Clock Buffer 350MHz | TI
MPN: LMK00804BQWRGTRQ1 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1.95 | $1.95 |
| 10 | $1.76 | $17.60 |
| 100 | $1.45 | $145.00 |
| 500 | $1.22 | $610.00 |
| 1,000 | $1.02 | $1,020.00 |
Drop-in alternatives for LMK00804BQWRGTRQ1 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
LMK00804BQWRGTR
β Drop-Inπ Reference alternative (not in catalog)
LMK00804BQWRGTTQ1
β Drop-Inπ Reference alternative (not in catalog)
LMK00804BWRGTRQ1
β Drop-Inπ Reference alternative (not in catalog)
LMK00804BQWRGTRQ1 Maximum Ratings & Electrical Characteristics
| Function | 1-to-4 LVCMOS fan-out buffer and level translator |
| Maximum Input Frequency | 350 MHz |
| Number of Outputs | 4 |
| Number of Inputs | 2 (selectable) |
| Input Type | Differential or single-ended (LVCMOS/LVTTL) |
| Output Type | LVCMOS |
| Output Level Options | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| Supply Voltage Range | 1.5 V to 3.3 V |
| Glitchless Enable | Yes (synchronized clock enable) |
| Qualification | AEC-Q100 automotive grade |
| Package | 16-VFQFN exposed pad (RGTR) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +125C (automotive) |
| Additive Jitter | [DATA_NEEDED: additive jitter RMS] |
| Output Skew | [DATA_NEEDED: output skew] |
| RoHS Status | Compliant |
LMK00804BQWRGTRQ1 Pin Configuration
| Pin 1 | VDD β Core power supply, 1.5V to 3.3V |
| Pin 2 | CLKIN0 β Clock input 0 (single-ended or differential P) |
| Pin 3 | CLKIN0_N β Differential complement input 0 (or GND for single-ended) |
| Pin 4 | CLKIN1 β Clock input 1 (single-ended or differential P) |
| Pin 5 | CLKIN1_N β Differential complement input 1 |
| Pin 6 | CLK_SEL β Input select between CLKIN0 and CLKIN1 |
| Pin 7 | CLK_EN β Synchronized clock enable, glitchless |
| Pin 8 | GND β Ground |
| Pin 9 | OUT0 β LVCMOS clock output 0 |
| Pin 10 | OUT1 β LVCMOS clock output 1 |
| Pin 11 | OUT2 β LVCMOS clock output 2 |
| Pin 12 | OUT3 β LVCMOS clock output 3 |
| Pin 13 | VDDO β Output driver supply, sets output level 1.5V-3.3V |
| Pin 14 | VDDO β Output driver supply |
| Pin 15 | NC β No connect [DATA_NEEDED: exact pin map] |
| Pin 16 | PAD β Exposed thermal pad, connect to GND |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
LMK00804BQWRGTRQ1 is suitable for 6 applications: Automotive Infotainment Clock Distribution, ADAS Sensor Hub Clocking, Industrial PLC and Motor Drive Control Cards, Networking and Telecom Line Cards, Test and Measurement Instrument Timing, Server and Storage Backplane Clock Fan-out.
Automotive Infotainment Clock Distribution
The LMK00804BQWRGTRQ1 distributes a single oscillator reference to SoCs, audio codecs, and display serializers in automotive infotainment head units. Its AEC-Q100 qualification and -40C to +125C range satisfy automotive environmental requirements, while the B-version die minimizes additive jitter so audio and video clocks remain clean. The glitchless synchronized enable lets the system gate clocks safely during power-mode transitions, and VDDO-based level translation bridges 1.8V processor domains to 3.3V peripheral rails up to 350 MHz without external translators.
Recommended
ADAS Sensor Hub Clocking
In ADAS domains, radar, camera, and lidar subsystems need phase-coherent clocks from one reference. The LMK00804BQWRGTRQ1 fans out a 25 MHz or 100 MHz reference to four loads with matched output skew, keeping the radar chirp and camera frame timing aligned. Its 350 MHz ceiling covers modern high-frequency references, and differential input acceptance lets it sit directly on an LVDS/LVPECL-derived single-ended tap. The 16-VFQFN exposed pad provides the solid ground return needed for low-jitter operation in electrically noisy vehicular environments.
Recommended
Industrial PLC and Motor Drive Control Cards
Industrial controllers using C2000 MCUs and FPGAs require multiple copies of a system clock across isolation and interface circuitry. The LMK00804BQWRGTRQ1 fans out one reference to the MCU, FPGA, and communication PHYs, and its level translation drives 3.3V logic from a 1.8V oscillator or vice versa. Although automotive-qualified, its wide temperature range and robustness equally benefit factory-floor temperature swings. The glitchless enable is valuable when control cards hot-swap clock domains during firmware updates or redundant-controller failover.
Recommended
Networking and Telecom Line Cards
Line cards must distribute a recovered or synthesized reference to Ethernet PHYs, retimers, and serializers. The LMK00804BQWRGTRQ1 provides four low-skew LVCMOS copies of a single reference, with the selectable dual input enabling automatic failover between a primary and backup reference clock. The 350 MHz input range covers 156.25 MHz and 322.26 MHz class references used in 10G/25G designs, and the level translator adapts 1.8V PHY outputs to 3.3V legacy loads, simplifying mixed-voltage board design.
Recommended
Test and Measurement Instrument Timing
Bench instruments and automated test equipment distribute a master reference to ADCs, FPGAs, and trigger logic. The B-version LMK00804B low additive jitter preserves sample-clock purity for the precision ADCs in the signal chain, while matched output skew keeps multi-channel acquisition synchronized. The dual selectable input supports switching between an internal ovenized reference and an external 10 MHz input, and the glitchless enable avoids spurious trigger events when references change. Wide 1.5V-to-3.3V output levels interface directly with mixed-voltage measurement front ends.
Recommended
Server and Storage Backplane Clock Fan-out
Server and storage systems replicate a baseboard reference across NVMe controllers, BMCs, and switch ASICs. The LMK00804BQWRGTRQ1 fans out one reference to four clock loads with minimal skew, and its selectable dual inputs support failover between a main clock generator and a hot-spare. The 16-VFQFN small footprint fits dense clock-tree routing zones on backplanes, and the 3.3V output level directly drives legacy PCI-style loads while 1.8V outputs serve modern silicon. RoHS-compliant construction suits high-volume datacenter hardware.
Recommended
Recommended Products Summary
Engineering reference data for LMK00804BQWRGTRQ1 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LMK00804BQWRGTR | LMK00804BQWRGTTQ1 | LMK00804BWRGTRQ1 |
|---|---|---|---|---|
| Package | 16-VFQFN exposed pad (RGTR) | 16-VFQFN exposed pad - same | 16-VFQFN exposed pad - same | 16-VFQFN exposed pad - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Output Configuration | 1:4 LVCMOS | 1:4 LVCMOS | 1:4 LVCMOS | 1:4 LVCMOS |
| Max Frequency | 350 MHz | 350 MHz | 350 MHz | 350 MHz |
| AEC-Q100 Qualified | Yes (-Q1) | No (industrial grade) | Yes (-Q1) | Yes (-Q1) |
| Level Translation | 1.5V-3.3V outputs | 1.5V-3.3V outputs | 1.5V-3.3V outputs | 1.5V-3.3V outputs |
| Glitchless Enable | Yes | Yes | Yes | Yes |
| Packaging Quantity | 3000 (Tape & Reel) | 3000 (Tape & Reel) | 250 (Tape & Reel) | [DATA_NEEDED] |
Key Differentiators
- Automotive AEC-Q100 qualification (vs LMK00804BQWRGTR)
- B-version die with improved jitter (vs LMK00804-Q1 (original))
- Prototype-friendly small reel option (vs LMK00804BQWRGTRQ1 (3000-reel))
Design Notes
Solder the exposed thermal pad of the 16-VFQFN package directly to a solid ground plane with a 3x3 via array. This pad is the primary ground return for the four LVCMOS output drivers; a poor pad connection raises ground bounce and degrades output-to-output skew and additive jitter. Keep output traces 50-ohm controlled impedance when driving long traces, and length-match outputs that feed phase-sensitive loads.
Decouple each VDD and VDDO pin with 0.1uF X7R ceramics placed within 2 mm of the pins, plus one 4.7uF bulk capacitor per supply rail. Use a dedicated low-noise LDO for VDDO when driving sensitive loads, since output switching current modulates VDDO directly; the output level equals VDDO. Avoid routing switching-regulator ripple under the clock traces.
For single-ended operation, terminate the unused differential complement (CLKINx_N) per the datasheet recommendation - floating it causes input-threshold chatter and glitched outputs. When using CLK_SEL between asynchronous inputs, expect momentary phase discontinuity; the glitchless enable only protects the CLK_EN gating, not input switching while running.
Compliance Information
AEC-Q100 qualified per TI product page (-Q1 suffix). RoHS and lead-free per DigiKey listing; REACH/halogen details not present in provided data.
