M25P40-VMP6TGB - 4Mb SPI NOR Flash 75MHz VFQFPN-8 | Micron
MPN: M25P40-VMP6TGB ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.85 | $2.85 |
| 10 | $2.55 | $25.50 |
| 100 | $2.1 | $210.00 |
| 500 | $1.78 | $890.00 |
| 1,000 | $1.45 | $1,450.00 |
M25P40-VMP6TGB Overview
A serial NOR Flash is a non-volatile memory that stores data persistently and communicates with a host controller over a low-pin-count synchronous protocol such as SPI. Within the memory hierarchy, NOR Flash sits between EPROM/EEPROM and NAND Flash: it offers random byte-level read access like EEPROM but at much higher density, and unlike NAND it supports execute-in-place (XiP) directly from the array. This part belongs to the SPI NOR Flash family, the dominant standard for boot, configuration, and firmware storage in microcontrollers, FPGAs, and consumer devices.
Key features include Page Program of up to 256 bytes in 0.8 ms (typical), Sector Erase of 512 Kbit in 0.6 s (typical), and Bulk Erase of the full 4 Mbit in 4.5 s (typical). Deep Power-down mode draws only 1 uA (typical), and Hardware Write Protection is configurable through three non-volatile bits (BP0, BP1, BP2) to lock out a defined protected area. The single 2.3-3.6 V supply simplifies integration with 3.3 V MCUs and 3 V FPGAs.
The device is organized as 512 K x 8 with an 8 ns access time, implemented as a NOR architecture with hardware-accelerated page programming and sector-erase blocks. The 75 MHz SPI clock supports fast code-shadowing and XiP boot, while the deep power-down mode enables battery-friendly idle states. The VFQFPN-EP package provides a low thermal-resistance path and a compact footprint for space-constrained designs.
Typical applications include boot and firmware storage for microcontrollers and FPGAs, IoT and smart-home sensor hubs, industrial control and metering, automotive infotainment and cluster code storage, and consumer electronics such as set-top boxes and printers. The 4 Mbit density is well suited to small boot images, lookup tables, and parameter sets.
When designing with this device, ensure the host SPI controller supports the JEDEC-standard SFDP-less instruction set (READ, PAGE PROGRAM, SECTOR ERASE, BULK ERASE, READ-ID, READ-STATUS) and that CS# is returned high between commands. Decouple VCC with a 100 nF ceramic capacitor close to the pin and observe the datasheet timing for tSE and tBE during in-application updates.
This page synthesizes distributor pricing, drop-in alternates from the same M25P40 family and cross-brand SPI NOR alternatives, pinout, and practical design notes that go beyond a generic datasheet summary.
Drop-in alternatives for M25P40-VMP6TGB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
M25P40-VMP6TGB
✅ Drop-In✓ In Stock
$1.45 / Unit
View Datasheet →M25P40-VMP6GB
✅ Drop-In📋 Reference alternative (not in catalog)
M25P40-VMP6TG
✅ Drop-In📋 Reference alternative (not in catalog)
W25Q40BWUXIP
✅ Drop-In📋 Reference alternative (not in catalog)
AT25F512B
✅ Drop-In📋 Reference alternative (not in catalog)
M25P40-VMP6TGB Maximum Ratings & Electrical Characteristics
| Memory Type | Non-Volatile |
| Memory Format | FLASH - NOR |
| Memory Size | 4 Mbit (512 K x 8) |
| Interface | SPI (Serial) |
| Clock Frequency (max) | 75 MHz |
| Access Time | 8 ns |
| Supply Voltage | 2.3 V to 3.6 V |
| Page Program (typ.) | 0.8 ms (up to 256 bytes) |
| Sector Erase (typ.) | 0.6 s (512 Kbit) |
| Bulk Erase (typ.) | 4.5 s (4 Mbit) |
| Deep Power-down Current (typ.) | 1 uA |
| Write Protection | Hardware via BP0/BP1/BP2 |
| Operating Temperature | -40C to +85C |
| Package | VFQFPN-EP 8-pin (MLP8, 6x5 mm) |
| Mounting Type | Surface Mount (Tape & Reel) |
| RoHS Status | Compliant |
M25P40-VMP6TGB Pin Configuration
| Pin 1 | CS# — Chip Select (active low) |
| Pin 2 | DO (SO/MISO) — Serial Data Output |
| Pin 3 | W# (WP#) — Write Protect (active low) |
| Pin 4 | GND — Ground |
| Pin 5 | DI (SI/MOSI) — Serial Data Input |
| Pin 6 | CLK — Serial Clock |
| Pin 7 | HOLD# / RESET# — Hold or Reset (selected by non-volatile bit) |
| Pin 8 | VCC — Power Supply (2.3 V to 3.6 V) |
| Pin EP | EP — Exposed Pad (connect to GND for thermal dissipation) |
Typical Applications
M25P40-VMP6TGB is suitable for 7 applications: MCU Boot Flash Storage, FPGA Configuration Memory, Industrial Sensor Hub, IoT Smart-Home Gateway, Automotive Cluster Code Storage, Consumer Set-Top Box Firmware, Smart Meter Data Logging.
MCU Boot Flash Storage
The M25P40-VMP6TGB is well-suited for MCU boot flash storage thanks to its 75 MHz SPI bus and 512 K x 8 organization, which lets an 8/32-bit MCU shadow its firmware in a single SPI transaction at boot. At 2.3-3.6 V single supply, the device powers directly from the same 3.3 V rail as the MCU, eliminating level shifters. The 0.8 ms typical page-program and 0.6 s sector-erase times support fast in-field firmware updates. The 1 uA deep-power-down current keeps quiescent draw negligible in battery-backed boot designs, while the BP0/BP1/BP2 hardware write protection secures the boot sector against accidental overwrite.
Recommended
FPGA Configuration Memory
The M25P40-VMP6TGB serves as FPGA configuration memory where the SPI bus clocks a configuration bitstream up to 75 MHz, while the 4 Mbit density is enough to hold a small to medium FPGA bitstream for low-density FPGAs. The 2.3-3.6 V supply aligns with most 3.3 V FPGA configuration banks, simplifying PCB power design. The 8 ns access time matches the typical FPGA config-clock read latency, and the 1 uA deep-power-down current supports low-power FPGA standby states. Hardware write-protect via BP0-BP2 prevents accidental bitstream corruption during field updates.
Recommended
Industrial Sensor Hub
For industrial sensor hub designs, the M25P40-VMP6TGB provides reliable 4 Mbit non-volatile storage for sensor calibration tables, alarm thresholds, and event logs. The 2.3-3.6 V supply is compatible with 24 V industrial bus rails regulated down to 3.3 V. Wide -40C to +85C operation tolerates factory-floor temperatures, and the SPI bus at 75 MHz lets a small Cortex-M0+ host refresh calibration data quickly. The 0.6 s sector-erase time and 0.8 ms page-program enable periodic field updates, while hardware write-protect keeps factory calibration immutable once BP0-BP2 are programmed.
Recommended
IoT Smart-Home Gateway
In IoT smart-home gateways, the M25P40-VMP6TGB stores the Wi-Fi/BLE pairing credentials, device database, and OTA staging image. The 1 uA deep-power-down mode is critical for battery-backed gateway standby, while the 75 MHz SPI supports fast OTA image writes. The 8 ns access time keeps boot latency low, and the VFQFPN-EP 6x5 mm footprint fits inside small enclosure layouts. The hardware write-protect via BP0-BP2 can lock factory credentials while leaving user-data sectors free to be updated.
Recommended
Automotive Cluster Code Storage
In automotive cluster and infotainment subsystems, the M25P40-VMP6TGB holds the gauge-cluster boot image and small GUI assets. Although this part is not AEC-Q100 qualified, its -40C to +85C operating range and 2.3-3.6 V supply cover many cabin-electronics environments. The 75 MHz SPI supports fast cluster power-up, while the BP0/BP1/BP2 bits protect the boot sector from corruption during service-mode updates. The VFQFPN-EP 6x5 mm footprint is compatible with mainstream automotive PCB assembly processes.
Recommended
Consumer Set-Top Box Firmware
For consumer set-top boxes and DVR peripherals, the M25P40-VMP6TGB stores the bootloader, kernel image, and persistent UI settings. The 4 Mbit density is sufficient for small Linux initramfs images and configuration blobs. The 2.3-3.6 V single supply aligns with standard STB 3.3 V rails, and the 75 MHz SPI keeps boot time under a second. The 1 uA deep-power-down supports STB standby power regulations (Energy Star). BP0/BP2 write-protect keeps the bootloader immutable while data sectors remain rewritable.
Recommended
Smart Meter Data Logging
In smart-meter designs, the M25P40-VMP6TGB retains the energy-consumption log, cryptographic keys, and tariff tables across power outages. Its 4 Mbit capacity stores weeks of metering intervals at 15-minute resolution, while the 2.3-3.6 V supply works with battery-backed 3.6 V lithium cells. The 1 uA deep-power-down keeps quiescent drain negligible during blackouts, and the 0.6 s sector-erase supports periodic log-rotation cycles. The BP0/BP1/BP2 bits can lock cryptographic keys permanently.
Recommended
Recommended Products Summary
Engineering reference data for M25P40-VMP6TGB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | M25P40-VMP6TGB | M25P40-VMP6GB | M25P40-VMP6TG | W25Q40BWUXIP | AT25F512B |
|---|---|---|---|---|---|---|
| Brand | Micron Technology | Micron Technology | Micron Technology | Micron Technology | Winbond | Adesto Technologies |
| Package | VFQFPN-EP 8 (MLP8, 6x5 mm) | VFQFPN-EP 8 - same | VFQFPN-EP 8 - same | VFQFPN-EP 8 - same | USON-8 6x5 mm - footprint compatible | WSON-8 6x5 mm - footprint compatible |
| Memory Size | 4 Mbit (512 K x 8) | 4 Mbit | 4 Mbit | 4 Mbit | 4 Mbit | 512 Kbit (-87.5%) |
| Interface | SPI 75 MHz | SPI 75 MHz | SPI 75 MHz | SPI 75 MHz | SPI 104 MHz | SPI 70 MHz |
| Supply Voltage | 2.3 V to 3.6 V | 2.3 V to 3.6 V | 2.3 V to 3.6 V | 2.3 V to 3.6 V | 2.3 V to 3.6 V | 2.3 V to 3.6 V |
| Sector Erase Time | 0.6 s typical | 0.6 s | 0.6 s | 0.6 s | 0.4 s | 0.6 s |
| Page Program Time | 0.8 ms typical | 0.8 ms | 0.8 ms | 0.8 ms | 0.7 ms | 0.5 ms |
| Deep Power-down Current | 1 uA typical | 1 uA | 1 uA | 1 uA | 1 uA | 2 uA |
| Write Protection | Hardware BP0/BP1/BP2 | Hardware BP0/BP1/BP2 | Hardware BP0/BP1/BP2 | Hardware BP0/BP1/BP2 | Hardware + Software lock | Hardware + Software lock |
| Lifecycle | Obsolete | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Active | Active |
Key Differentiators
- Single 2.3-3.6 V supply with no level shifter required (vs AT25F512B)
- 75 MHz SPI bus for fastest legacy Micron-class boot speeds (vs AT25F512B (70 MHz SPI))
- Hardware BP0/BP1/BP2 lockable write protection (vs W25Q40BWUXIP)
- Industry-standard VFQFPN-EP 6x5 mm package shared across 4 Mbit/Flow families (vs M25P40-VMN3PB (SO-8))
Design Notes
Place a 100 nF ceramic decoupling capacitor as close as possible between the VCC pin (8) and GND (4). The exposed pad (EP) MUST be soldered to a ground plane to meet the 31.4 C/W theta-JA rating. Route the SPI bus signals (CS#, CLK, DI, DO) with matched lengths and a series 33 ohm resistor near the host to dampen ringing at 75 MHz - signal-integrity is the most common cause of intermittent boot failures.
At 75 MHz SPI clock, the CS#, CLK, and SI lines should be treated as 50 ohm controlled-impedance traces. Estimated: stub length should be < 3 mm, and CLK rise time is ~2 ns at the part input. Place a 22-33 ohm series damping resistor at the driver output if the cable/trace exceeds 25 mm total length. DO is push-pull and may be left un-terminated if the trace is short.
The HOLD# and RESET# functions share pin 7 - selection is made by a non-volatile configuration bit that is FOOLED at factory. Designers who try to drive pin 7 high expecting a hold operation will instead trigger a reset if the device was factory-set to RESET mode. Check the status-register non-volatile configuration byte before wiring pin 7 to a host GPIO. Likewise, ensure CS# is de-asserted high between commands - leaving CS# low between sectors can cause the part to enter an unexpected command state.
Keep the SPI bus away from switching DC-DC converter nodes and high-current traces. The 8 ns access time means the part is sensitive to noise on VCC during read cycles - large VCC droops above 50 mV can trigger an internal brown-out and abort the read, producing CRC errors in the boot image. A 4.7 uF bulk capacitor adjacent to the VCC pin plus a 100 nF high-frequency cap gives 60 dB of PSRR across the SPI clock bandwidth.
Compliance Information
RoHS compliant per Micron product page. Not AEC-Q100 qualified - do not use for automotive safety-critical applications.
