MCIMX6D5EYM10AC - i.MX6Dual 1GHz ARM Cortex-A9 MPU | NXP
MPN: MCIMX6D5EYM10AC ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.92 | $38.92 |
| 10 | $35.74 | $357.40 |
| 100 | $31.55 | $3,155.00 |
| 500 | $27.98 | $13,990.00 |
| 1,000 | $25.16 | $25,160.00 |
MCIMX6D5EYM10AC Overview
An applications processor (AP) is a highly-integrated system-on-chip (SoC) designed for multimedia and human-machine-interface (HMI) workloads. It sits above microcontrollers in the embedded processing hierarchy and below desktop CPUs in raw performance, combining CPU cores, GPU, memory controller, display controllers, and a rich peripheral set on a single die. The i.MX6 family further refines this concept with smart speed technology that scales voltage and frequency per domain to optimize power consumption.
Key features of the MCIMX6D5EYM10AC include 1080p60 video decode/encode via the integrated multi-format video codec, a 3D-capable GPU (Vivante GC2000 plus GC355 plus GC320), dual-display support up to WUXGA+WXGA, dual-lane MIPI-DSI and MIPI-CSI interfaces, SATA-II (3 Gbps), PCI Express Gen 2.0, USB OTG with PHY, and a wide peripheral mix including Gigabit Ethernet, MLB150, and multiple UART/I2C/SPI ports. The -EYM10AC suffix denotes the industrial-grade 1.0 GHz dual-core variant in FCPBGA-624.
Architecturally the part uses a 40 nm process with a 64-bit DDR3/LPDDR2 memory controller supporting up to 2 GB of addressable memory. A multi-level memory system (L1 + L2 + NEON) and dedicated smart-speed domains let the cores, GPU, and IP blocks run at independent DVFS curves, which is critical for fanless industrial designs.
Typical applications include industrial HMI panels, automotive infotainment, medical imaging terminals, factory-automation controllers, digital signage, and ruggedized single-board computers. The wide operating temperature range and ECC support on the DDR interface make it suitable for harsh environments.
Designers should plan a 4-layer or 6-layer PCB with the controlled-impedance DDR routing required by the i.MX6 and provide a dedicated PMIC such as the NXP PF3000/PF3001 to supply the multi-rail core/SoC/GPU sequencing. The 624-ball package also demands strict via-in-pad and microvia stackup adherence.
This page synthesizes distributor pricing, lifecycle status, drop-in alternatives from the same i.MX6 family, and PCB/design notes not found in the manufacturer datasheet - giving the engineer a single, decision-ready view of the part.
Drop-in alternatives for MCIMX6D5EYM10AC — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MCIMX6D5EYM10AC (same form factor and footprint) — differing in Display Interfaces, Mounting Type, Package, Series.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MCIMX6D5EYM12AD
✅ Drop-In📋 Reference alternative (not in catalog)
MCIMX6D6AVT10ADR
✅ Drop-In📋 Reference alternative (not in catalog)
MCIMX6D7CVT08AD
✅ Drop-In📋 Reference alternative (not in catalog)
MCIMX6D5EYM10AD
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MCIMX6Q4AVT10AC
✅ Drop-In✓ In Stock
$44.8 / Unit
View Datasheet →MCIMX6D5CYM10AD
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MCIMX6D5EYM10AC Maximum Ratings & Electrical Characteristics
| Product Type | Applications Processor / Microprocessor (MPU) |
| Series | i.MX 6Dual |
| Core Architecture | ARM Cortex-A9 (dual-core) |
| Operating Frequency | 1.0 GHz |
| Data Bus Width | 32-bit |
| Package | 624-FCPBGA (21x21 mm) |
| L1 Cache (I + D per core) | 32 KB + 32 KB |
| L2 Cache | 1 MB (shared) |
| Memory Controller | 64-bit DDR3 / LPDDR2, up to 2 GB |
| GPU | Vivante GC2000 + GC355 + GC320 |
| Video Codec | 1080p60 multi-format decode/encode |
| Display Interfaces | Dual-display WUXGA+WXGA, 2-lane MIPI-DSI |
| Camera Interface | 2-lane MIPI-CSI, parallel |
| Storage Interfaces | SATA-II (3 Gbps), SD/MMC, NAND |
| High-Speed I/O | PCIe Gen 2.0, USB OTG with PHY |
| Networking | Gigabit Ethernet, MLB150 |
| Operating Temperature | -40C to +105C (industrial) |
| Process Technology | 40 nm CMOS |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
MCIMX6D5EYM10AC Pin Configuration
| Pin A1 | VCC_ARM — ARM core supply (set by PMIC) |
| Pin B1 | GND — Ground reference |
| Pin C1 | DDR_DQ0 — DDR3 data lane 0 |
| Pin D1 | DDR_DQ1 — DDR3 data lane 1 |
| Pin E1 | DDR_DQS0_P — DDR3 data strobe 0 positive |
| Pin F1 | NVCC_DRAM — DDR3 I/O supply |
| Pin G1 | BOOT_MODE0 — Boot mode selection bit 0 |
| Pin H1 | POR_B — Power-on reset (active low) |
| Pin J1 | USB_OTG_DP — USB OTG data positive |
| Pin K1 | PCIe_REF_CLK_P — PCIe reference clock positive |
Typical Applications
MCIMX6D5EYM10AC is suitable for 6 applications: Industrial HMI Panels, Automotive Infotainment (Non-Safety), Medical Imaging Terminals, Digital Signage and Kiosks, Single-Board Computers (SBC) and IoT Gateways, Printer and Imaging MFP Controllers.
Industrial HMI Panels
The MCIMX6D5EYM10AC is widely used in industrial human-machine interface (HMI) panels for factory automation. Its dual Cortex-A9 cores at 1.0 GHz handle Qt/Linux HMI stacks with sufficient headroom for OPC-UA and Modbus-TCP, while the Vivante GC2000 GPU accelerates OpenGL ES 3.0 widget rendering. The dual-display pipeline drives a WUXGA primary panel and a WXGA status display simultaneously, and the -40C to +105C industrial temperature grade supports unprotected cabinet installations. ECC on the DDR3 interface catches memory faults in 24/7 operations, critical for SCADA and process-control panels where unplanned downtime is unacceptable.
Recommended
Automotive Infotainment (Non-Safety)
Although the -E part is industrial rather than automotive, the MCIMX6D5EYM10AC is sometimes used in aftermarket and commercial-vehicle infotainment systems where AEC-Q100 is not strictly mandated. The integrated 1080p60 multi-format video codec decodes H.264/MPEG-4 streams from the head unit's media stack, while the dual-display pipeline can drive a center-stack display plus an instrument-cluster TFT. Designers targeting OEM automotive should migrate to the pin-compatible MCIMX6D6AVT10ADR (AEC-Q100 qualified) without changing the PCB layout.
Recommended
Medical Imaging Terminals
The MCIMX6D5EYM10AC suits medical imaging terminals such as portable ultrasound carts, patient-monitoring bedside stations, and endoscopy video processors. The Cortex-A9 NEON SIMD engine accelerates image-processing kernels (filtering, FFT, edge detection) at 1.0 GHz, while the dual-MIPI-CSI inputs accept two image sensors in parallel for stereo or dual-view endoscopy. The hardware multi-format codec captures and stores 1080p60 procedure video to SATA-II storage at 3 Gbps. While the part is not FDA-cleared, its long-term availability and NXP's medical-grade change-notice policy make it a common platform in non-life-support medical devices.
Recommended
Digital Signage and Kiosks
Retail digital signage, self-service kiosks, and vending-machine HMIs benefit from the MCIMX6D5EYM10AC's combination of dual-display support, hardware video decode, and low thermal output. The GC2000 GPU drives OpenGL ES animations on the customer-facing display while a second screen delivers interactive touch menus. The PCIe Gen 2.0 interface accepts Wi-Fi 5/6 NICs for cloud content updates, and SATA-II supports a local SSD cache for offline playback. A 6-layer PCB plus the NXP PF3000 PMIC enables fanless kiosk enclosures, reducing MTBF-impacting moving parts in 24/7 retail deployments.
Recommended
Single-Board Computers (SBC) and IoT Gateways
The MCIMX6D5EYM10AC is a popular CPU for fanless industrial single-board computers and IoT edge gateways that aggregate sensor data over Modbus, MQTT, or OPC-UA. The Gigabit Ethernet MAC plus MLB150 automotive bus interface let the same board serve both IT and OT networks. The industrial temperature range and ECC memory support make it suitable for outdoor gateways in energy distribution or rail signaling where ambient temperatures swing widely. Linux distributions (Yocto BSP, mainline kernel 5.x) are maintained by NXP and the community, easing long-term support.
Recommended
Printer and Imaging MFP Controllers
Office multifunction printers and large-format plotters leverage the MCIMX6D5EYM10AC for their main controller. The dual Cortex-A9 cores run the printer's job scheduler and raster image processor (RIP), the PCIe interface accepts networking cards, the SATA-II hosts a hard drive for job spooling, and the dual-display outputs drive the operator LCD plus the embedded web-server preview. The hardware video codec enables scan-to-MPEG preview thumbnails on the operator panel. NXP's 10+ year product longevity program has historically supported the office-equipment segment.
Recommended
Recommended Products Summary
Engineering reference data for MCIMX6D5EYM10AC — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MCIMX6D5EYM12AD | MCIMX6D6AVT10ADR | MCIMX6D7CVT08AD | MCIMX6Q4AVT10AC | MCIMX6D5CYM10AD |
|---|---|---|---|---|---|---|
| Package | 624-FCPBGA (21x21 mm) | 624-FCPBGA (21x21 mm) - same | 624-FCPBGA (21x21 mm) - same | 624-FCPBGA (21x21 mm) - same | 624-FCPBGA (21x21 mm) - same | 624-FCPBGA (21x21 mm) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| CPU Cores | 2x ARM Cortex-A9 | 2x ARM Cortex-A9 - same | 2x ARM Cortex-A9 - same | 2x ARM Cortex-A9 (Plus) - same | 4x ARM Cortex-A9 - +100% cores | 2x ARM Cortex-A9 - same |
| Operating Frequency | 1.0 GHz | 1.2 GHz (+20%) | 1.0 GHz - same | 0.8 GHz (-20%) | 1.0 GHz - same | 1.0 GHz - same |
| Automotive Qualification | No (industrial) | No (industrial) | Yes (AEC-Q100) | Yes (AEC-Q100) | Yes (AEC-Q100) | No (commercial) |
| Operating Temperature | -40C to +105C (industrial) | -40C to +105C (industrial) | -40C to +125C (automotive) | -40C to +125C (automotive) | -40C to +125C (automotive) | 0C to +95C (commercial) |
| Lifecycle Status | NRND | Active | Active | Active | Active | NRND |
| GPU Configuration | GC2000 + GC355 + GC320 | GC2000 + GC355 + GC320 - same | GC2000 + GC355 + GC320 - same | GC2000+ + GC355 + GC320 (enhanced) | GC2000 + GC355 + GC320 - same | GC2000 + GC355 + GC320 - same |
Key Differentiators
- True pin-compatible 1.2 GHz upgrade path remains in active production (vs MCIMX6D5EYM12AD)
- Pin-compatible migration to AEC-Q100 automotive grade (vs MCIMX6D6AVT10ADR)
- Lower price than Plus or Quad variants (vs MCIMX6Q4AVT10AC)
- Industrial temperature grade at lower cost than automotive (vs MCIMX6D6AVT10ADR)
Design Notes
The MCIMX6D5EYM10AC requires a multi-rail PMIC such as the NXP PF3000 or PF3001. Power-up sequencing is mandated by the datasheet: VCC_ARM (1.1V core) must rise before or simultaneously with VCC_SOC (1.0V SoC) and GPU rail. Failure to meet sequencing can cause permanent latch-up. Decoupling: place 0.1uF X7R 0402 capacitors within 2 mm of every VCC pin, plus 4.7uF bulk on each rail. Estimated worst-case power dissipation at 1.0 GHz dual-core full load: ~3.5 W; budget the thermal solution accordingly.
The 624-FCPBGA uses 0.8 mm ball pitch on a 21x21 mm body. PCB fabrication must support via-in-pad with filled-and-capped microvias to escape the inner-row balls. Use a 6-layer 1.55 mm stackup with controlled-impedance layers (50 ohm SE, 90 ohm diff) for DDR3, PCIe, USB, and HDMI routing. Route DDR3 address/command traces on layer 3 with reference to GND plane; route the data/strobe byte lanes length-matched within +/-25 mil. Follow NXP's i.MX6 Hardware Design Guide for layer stack and trace geometry.
At 1.0 GHz dual-core full load the MCIMX6D5EYM10AC dissipates an estimated 3.0-3.5 W with industrial junction-to-ambient thermal resistance around 25 C/W on a 6-layer PCB (per NXP SABRE board measurements). For fanless industrial enclosures, attach a 30x30x10 mm heatsink with thermal interface material, or use the top-exposed pad area (if available) with copper coin. In ambient above 85C, derate the CPU frequency to 800 MHz via DVFS in the BSP thermal governor to maintain the 105C junction limit.
Three common pitfalls with the MCIMX6D5EYM10AC: (1) Using an incorrect boot-mode fuse setting - the BOOT_MODE[1:0] pins and eFUSE configuration determine whether the part boots from SD, NAND, SPI, or SATA. Confirm the fuse map matches the production image before locking. (2) Forgetting the 32.768 kHz RTC crystal load capacitor values - the on-chip RTC oscillator is sensitive to stray capacitance; use NXP's reference 12.5 pF. (3) Ignoring the JTAG TRST pin - it must be pulled low through 4.7 kohm at power-up for the TAP controller to reset correctly.
DDR3 routing on the MCIMX6D5EYM10AC must follow strict length-matching rules: data byte lanes matched to +/-25 mil within a byte and +/-50 mil between bytes; address/command matched to +/-100 mil. Place the DDR3 chips on the same side of the PCB as the i.MX6 to minimize via count. Use fly-by topology for multi-rank DDR3 with series termination on address/command lines. PCIe Gen 2.0 routing requires 90 ohm differential impedance with intra-pair skew below 5 mil. Reference the NXP i.MX6 SABRE-SDP PCB design files for stackup and geometry.
Compliance Information
RoHS and REACH compliant per NXP product specifications. AEC-Q100 NOT qualified - migrate to MCIMX6D6AVT10ADR for automotive. Lead-free FCPBGA uses SAC405 solder balls.
