MT25QU128ABB1ESE-0AUT - 128Mb 1.8V Quad SPI NOR Flash | Micron
MPN: MT25QU128ABB1ESE-0AUT β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.2 | $3.20 |
| 10 | $2.95 | $29.50 |
| 100 | $2.6 | $260.00 |
| 500 | $2.35 | $1,175.00 |
| 1,000 | $2.1 | $2,100.00 |
Drop-in alternatives for MT25QU128ABB1ESE-0AUT β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
MT25QL128ABB1ESE-0AUT
β Drop-Inβ In Stock
$2.1 / Unit
View Datasheet βMT25QU256ABB1ESE-0AUT
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
MT25QL256ABB1ESE-0AUT
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
MT25QU128ABB1ESE-0AUT Maximum Ratings & Electrical Characteristics
| Density | 128 Mbit (16 MB) |
| Organization | 16M x 8 |
| Memory Type | Serial NOR Flash, SLC |
| Interface | SPI - Quad I/O |
| Maximum Clock Frequency | 166 MHz |
| Supply Voltage | 1.7 V to 2.0 V (1.8 V nominal) |
| Package | 8-SOIC 208 mil (SOP-2, ESE) |
| Mounting Type | Surface Mount |
| Speed Grade | -0AUT |
| Sector Erase Granularity | 4 KB, 32 KB, 64 KB |
| Operating Modes | Standard, Dual Output, Dual I/O, Quad Output, Quad I/O SPI |
| Supply Voltage Max | 2.0 V |
| Supply Voltage Min | 1.7 V |
| Packaging Option | Tray (ESE-0AUT) / Tape & Reel (ESE-0AUT TR) |
MT25QU128ABB1ESE-0AUT Pin Configuration
| Pin 1 | CS# β Chip select (active low) |
| Pin 2 | SO/SIO1 β Serial data output / quad I/O 1 |
| Pin 3 | WP#/SIO2 β Write protect (active low) / quad I/O 2 |
| Pin 4 | VSS β Ground |
| Pin 5 | SI/SIO0 β Serial data input / quad I/O 0 |
| Pin 6 | SCLK β Serial clock input |
| Pin 7 | RESET#/HOLD#/SIO3 β Hardware reset / hold / quad I/O 3 (multiplexed) |
| Pin 8 | VCC β Power supply, 1.7 V to 2.0 V |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
MT25QU128ABB1ESE-0AUT is suitable for 6 applications: FPGA Configuration Storage, Embedded Boot Code Storage, Networking and Communication Equipment, Automotive and Industrial Electronics, IoT and Smart Home Devices, Test and Measurement Instrumentation.
FPGA Configuration Storage
The MT25QU128ABB1ESE-0AUT is a primary choice for storing FPGA bitstreams, including Xilinx and Microchip (PolarFire/RTAX-class) configuration images. Its 128 Mb density holds large-bitstream devices with headroom for golden-fallback images, and the 166 MHz Quad SPI interface shortens configuration time significantly versus 1-bit SPI flashes. The 1.7 V to 2.0 V rail matches modern 1.8 V FPGA banks, eliminating level shifters between flash and FPGA. The multiplexed RESET#/SIO3 pin supports both daisy-chained quad reads and hard reset during power sequencing. Designers should verify the configuration-clock divider so the FPGA's CCLK meets the flash's 166 MHz maximum in quad-fast-read mode.
Recommended
Embedded Boot Code Storage
Boot ROM and first-stage loader images for application processors and microcontrollers are routinely stored in serial NOR because of its true random-access read and high reliability. The MT25QU128ABB1ESE-0AUT provides 16 MB of SLC storage at 1.8 V, sufficient for multi-stage bootloaders plus OTA recovery images. Quad-I/O fast reads at up to 166 MHz minimize boot latency compared to 1-bit SPI NOR, an important consideration for products with strict power-on-to-live timing requirements. The 4 KB sector granularity allows fine-grained management of parameter blocks separate from the boot image. Firmware teams should configure the volatile quad-enable bit early in the boot path to unlock full read bandwidth.
Recommended
Networking and Communication Equipment
Routers, switches, and line cards use serial NOR for firmware, device trees, and configuration data. The MT25QU128ABB1ESE-0AUT's 128 Mb SLC density holds dual firmware banks for fail-safe OTA upgrades, and its 1.8 V operation reduces rail count in dense switching designs that already run 1.8 V logic. The 166 MHz Quad SPI throughput supports fast boot of control-plane processors, while deterministic NOR erase/program behavior suits logging to reserved 64 KB blocks. Systems designers should budget program-page time in their watchdog design and use the hardware RESET# (via SIO3 when not in quad mode) to recover the flash from bus-contention states during hot insertion or brownout events.
Recommended
Automotive and Industrial Electronics
The AUT designation on MT25QU128ABB1ESE-0AUT reflects Micron's automotive-ordering flow, and the MT25Q family is used in ECU code storage, ADAS subsystems, and industrial drives. SLC NOR storage provides the endurance and data retention margins required for long product lifetimes, and the wide 1.7 V to 2.0 V supply tolerates regulated 1.8 V rails derived from automotive 12 V networks. Random-access reads enable in-place execution of diagnostic code without RAM copying. Designers must confirm the temperature grade and AEC qualification level applicable to the -0AUT ordering code on Micron's part-detail page before use in safety-relevant positions, and should implement CRC verification of boot images at every power cycle.
Recommended
IoT and Smart Home Devices
Wi-Fi, BLE, and Zigbee gateways store firmware, certificates, and provisioning data in serial NOR. The MT25QU128ABB1ESE-0AUT's low 1.8 V supply matches modern IoT SoCs, and its low standby current profile suits battery-buffered and energy-harvesting designs. 16 MB of SLC storage accommodates two full firmware images plus secure-element provisioning data, enabling A/B OTA updates with rollback. The 4 KB sectors permit frequent key-value updates without erasing firmware blocks, extending effective product life. Engineers should implement wear-leveling on parameter sectors and use the HOLD# capability during partial power states to suspend transfers without losing address position.
Recommended
Test and Measurement Instrumentation
Oscilloscopes, signal generators, and logic analyzers store calibration tables, waveform presets, and instrument firmware in serial NOR. The MT25QU128ABB1ESE-0AUT provides 128 Mb of reliable SLC storage whose random-access behavior suits calibration lookup tables read at runtime. Its 1.8 V Quad SPI interface integrates cleanly with FPGA-based acquisition engines that already run 1.8 V banks, and 166 MHz quad reads keep preset-recall times low. The 64 KB erase blocks map neatly onto per-channel calibration records. Designers should reserve a write-protected block for factory calibration and use software status-register protection to prevent accidental corruption of calibration data in the field.
Recommended
Recommended Products Summary
Engineering reference data for MT25QU128ABB1ESE-0AUT β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MT25QL128ABB1ESE-0AUT | MT25QU256ABB1ESE-0AUT | MT25QL256ABB1ESE-0AUT |
|---|---|---|---|---|
| Package | 8-SOIC 208 mil (SOP-2) | 8-SOIC 208 mil (SOP-2) - same | 8-SOIC 208 mil (SOP-2) - same | 8-SOIC 208 mil (SOP-2) - same |
| Brand | Micron Technology | Micron Technology | Micron Technology | Micron Technology |
| Density | 128 Mbit (16 MB) | 128 Mbit (16 MB) | 256 Mbit (32 MB) | 256 Mbit (32 MB) |
| Supply Voltage | 1.7 V to 2.0 V | 2.7 V to 3.6 V | 1.7 V to 2.0 V | 2.7 V to 3.6 V |
| Max Clock Frequency | 166 MHz (Quad SPI) | 166 MHz | 166 MHz | 166 MHz |
| Interface | SPI - Quad I/O | SPI - Quad I/O | SPI - Quad I/O | SPI - Quad I/O |
| Sector Erase Granularity | 4 KB / 32 KB / 64 KB | 4 KB / 32 KB / 64 KB | 4 KB / 32 KB / 64 KB | 4 KB / 32 KB / 64 KB |
| Pinout | 8-pin SOP-2 (CS#, SO/SIO1, WP#/SIO2, VSS, SI/SIO0, SCLK, RESET#/SIO3, VCC) | Identical 8-pin SOP-2 | Identical 8-pin SOP-2 | Identical 8-pin SOP-2 |
| Price (qty 1, as of 2026-09-02) | $3.20 (indicative) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- 1.8 V native operation eliminates level shifting (vs MT25QL128ABB1ESE-0AUT)
- Full 166 MHz Quad SPI clock (vs Legacy 1-bit SPI NOR flashes)
- Trade-off: 128 Mb fixed density on SOP-2 (vs MT25QU256ABB1ESE-0AUT)
Design Notes
The QU suffix means a 1.7 V to 2.0 V supply. Do not connect VCC to 3.3 V even transiently - overvoltage during brownout of a shared 3 V rail is a common failure mechanism. Use a clean 1.8 V LDO or buck output with at least 100 nF ceramic decoupling directly at pin 8, plus a 4.7 uF bulk capacitor. If the host bus is 3.3 V, add level shifters or select the MT25QL128ABB1ESE-0AUT instead.
In quad mode, pins 2, 3, 5, and 7 carry data at up to 166 MHz. Keep the four SIO traces length-matched within a few millimeters and route over a continuous ground plane. Add 22-33 ohm series resistors near the flash on SCLK and SIO lines if traces exceed roughly 10 cm, to damp reflections. Verify setup/hold margins with the host controller at the maximum clock divider settings, especially on first-revision boards.
Pin 7 is multiplexed as RESET#/HOLD#/DQ3. If your firmware enables the QE bit for quad I/O, the pin becomes DQ3 - ensure the host actually drives it, or reads will fail in quad mode. Also confirm the volatile vs non-volatile quad-enable behavior: the volatile QE bit resets on power-up unless set from the non-volatile register, which can cause intermittent quad-mode failures after cycling power. Pull CS# high with a 10 kohm resistor during power-up to prevent bus contention and accidental writes.
Compliance Information
Compliance declarations for this ordering code must be confirmed on Micron's official part-detail page; AUT ordering designation relates to Micron automotive ordering flow, and AEC-Q100 qualification level must be verified there.
