SS06-0B00-00 - PEX88032B0-DB PCIe Switch IC | Broadcom | 32-Lane
MPN: SS06-0B00-00 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $369.53 | $369.53 |
| 10 | $355 | $3,550.00 |
| 100 | $320 | $32,000.00 |
| 500 | $295 | $147,500.00 |
| 1,000 | $270 | $270,000.00 |
SS06-0B00-00 Overview
A PCIe switch (Peripheral Component Interconnect Express switch) is a connectivity IC that fans out a single PCIe root-complex upstream port into multiple downstream ports while maintaining protocol-aware packet routing, credit-based flow control, and full PCIe Gen4/Gen5 link training. PCIe switches sit in the topology hierarchy: endpoint -> switch -> root complex, and they are essential building blocks for NVMe aggregators, GPU fabric expansion cards, and disaggregated composable infrastructure where compute and storage resources must be dynamically pooled. Broadcom's PEX88000 series is the industry's broadest PCIe switching portfolio and dominates enterprise server backplanes.
Key features of the SS06-0B00-00 include 32 PCIe lanes, support for common PCIe generations negotiated per port, hot-plug and surprise-add/remove handling, advanced error reporting (AER), and SR-IOV pass-through capability for virtualization. The device is fabricated in a low-power CMOS process and integrates Spread Spectrum Clock Isolation to ease mixed-clock-domain PCB design. It supports MCTP and SMBus management interfaces for out-of-band platform telemetry.
Architecturally, the PEX88032B0-DB uses a non-blocking cut-through switch fabric with internal buffering for up to packet-header credits per VC, enabling line-rate forwarding on all ports simultaneously. The switch complies with the PCI Express base specification and supports Access Control Services (ACS) for peer-to-peer traffic isolation, which is required in multi-tenant cloud environments.
Typical applications include NVMe storage aggregators (NVMe-oF over PCIe fabric), composable disaggregated infrastructure (CDI) backplanes, accelerator add-in cards that expose GPUs or FPGAs to multiple hosts, and high-port-count PCIe fan-out riser cards. The SS06-0B00-00 is also used in edge servers requiring dense PCIe expansion in a constrained thermal envelope.
When designing with this device, allocate adequate PCB area for the high-speed TX/RX lane routing, maintain differential pair length matching within the PCIe CEM specification tolerance, and ensure the auxiliary power rail sequencing respects the PCIe inrush specification. Reference firmware from Broadcom should be loaded via the external SPI flash for proper port configuration.
Drop-in alternatives for SS06-0B00-00 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SS06-0B00-00 (same form factor and footprint) — differing in RoHS Status, Hot-Plug Support, Management Interface, PCIe Generation, Package Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SS05-0B00-00
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Contact for price
View Datasheet →PEX88096B0-DB
✅ Drop-In✓ In Stock
$1145 / Unit
View Datasheet →SS06-0B00-00 Maximum Ratings & Electrical Characteristics
| Manufacturer | Broadcom |
| Internal Part Number | PEX88032B0-DB |
| Function | PCI Express Switch IC |
| Protocol Category | PCI Express (PCIe) |
| Total PCIe Lanes | 32 |
| Port Configuration | Configurable upstream/downstream ports (per firmware) |
| Process Technology | CMOS |
| JEDEC Package Code | X-XXSS-X (per Partstack entry) |
| Package Type | BGA (high-density substrate) |
| Maximum Operating Temperature | 70 C |
| Management Interface | I2C / SMBus / MCTP |
| Firmware Interface | External SPI flash |
| Hot-Plug Support | Yes |
| SR-IOV Support | Yes |
| Advanced Error Reporting (AER) | Yes |
| RoHS Status | Compliant |
| Reach Status | Compliant |
SS06-0B00-00 bga (high-density substrate) Pin Configuration Guide
Pin configuration for SS06-0B00-00 (bga (high-density substrate) package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for SS06-0B00-00.
Refer to the datasheet for full pin configuration.
Typical Applications
SS06-0B00-00 is suitable for 6 applications: NVMe Storage Aggregator, Composable Disaggregated Infrastructure (CDI) Backplane, GPU/FPGA Accelerator Add-In Card, Edge Server PCIe Riser Fan-Out, NVMe-over-Fabric (NVMe-oF) Target Adapter, PCIe Diagnostic and Protocol Analyzer Backplane.
NVMe Storage Aggregator
The Broadcom SS06-0B00-00 (PEX88032B0-DB) is well matched to NVMe storage aggregation because its 32 PCIe lanes, hot-plug support, and SR-IOV pass-through map directly onto the topology of a multi-host NVMe-over-PCIe chassis. The switch's cut-through forwarding fabric sustains line-rate read/write traffic on every lane simultaneously, which is essential when dozens of NVMe SSDs are exposed to one or more root complexes. Placed between the upstream host port and the downstream NVMe bays, the SS06-0B00-00 enables surprise-add/remove of drives without host reboot and isolates peer-to-peer traffic via Access Control Services. Compared with a software NVMe RAID controller, this hardware aggregation reduces host CPU utilization and lowers tail latency.
Recommended
Composable Disaggregated Infrastructure (CDI) Backplane
In composable disaggregated infrastructure, compute, storage, and accelerator resources are dynamically pooled over a PCIe fabric, and the Broadcom SS06-0B00-00 serves as the backplane switch. Its 32 configurable lanes can be partitioned into multiple upstream host ports and many downstream device ports, enabling any-to-any connectivity required by composable designs. The SS06-0B00-00's non-transparent bridging mode (where supported by firmware) lets separate processor domains address the same downstream resources without address conflicts. With the part operating at typical PCIe Gen4 data rates per lane, aggregate fabric bandwidth scales to satisfy modern GPU and NVMe workloads in hyperscale data centers.
Recommended
GPU/FPGA Accelerator Add-In Card
The SS06-0B00-00 enables a single accelerator card to expose multiple GPUs or FPGAs to one or more host root complexes, eliminating the need for a separate PCIe slot per accelerator. The switch's 32 lanes can be split as one x16 upstream plus two x8 downstream, allowing two accelerators to share the slot's bandwidth while maintaining independent SR-IOV virtual function isolation. This is valuable in dense PCIe slots where signal-integrity and BMC slot-count limits prevent direct multi-host connections. With hot-plug support, accelerators can be serviced without powering down the chassis, and the part's low-power CMOS process keeps the add-in card within typical 25 W auxiliary-power budgets.
Recommended
Edge Server PCIe Riser Fan-Out
Edge servers require dense PCIe expansion in a constrained thermal envelope, and the SS06-0B00-00 packs 32 lanes of switching into a single BGA that fits riser-card form factors. Its 70 C maximum operating temperature supports sealed edge chassis without forced airflow, while Broadcom's Spread Spectrum Clock Isolation eases mixed-clock-domain routing between the server SoC and the riser. The switch's firmware-configurable port widths let one riser design support multiple SKUs (e.g., x16 + 2x x8 or 4x x8) without PCB respins. Compared with discrete retimer/redriver cascades, the SS06-0B00-00 reduces component count and BOM cost while improving link-training reliability.
Recommended
NVMe-over-Fabric (NVMe-oF) Target Adapter
When implementing an NVMe-oF target adapter, the SS06-0B00-00 provides the PCIe fan-out that aggregates multiple NAND channels behind a single fabric port. The switch's high port count allows designers to connect several NVMe controller ASICs to one upstream host port while preserving peer-to-peer traffic isolation via ACS. With SR-IOV enabled, each virtual function maps to a discrete NVMe namespace, simplifying multi-tenant storage virtualization. The part's low-latency cut-through fabric minimizes NVMe command overhead compared with store-and-forward switches.
Recommended
PCIe Diagnostic and Protocol Analyzer Backplane
Test and measurement equipment that captures PCIe traffic across multiple lanes can use the SS06-0B00-00 as a programmable signal-fan-out element. Its ports can be toggled between upstream and downstream modes under firmware control, letting a single analyzer chassis mimic either an endpoint or a root complex. Combined with Broadcom's MCTP/SMBus management interface, the SS06-0B00-00 simplifies chassis management in production ATE environments where dozens of DUTs must be linked to a tester. The 32-lane budget matches PCIe Gen4 x16 plus Gen4 x8 probe channels with margin.
Recommended
Recommended Products Summary
Engineering reference data for SS06-0B00-00 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SS05-0B00-00 | PEX88096B0-DB |
|---|---|---|---|
| Package | BGA (JEDEC X-XXSS-X) | BGA (PEX88000 family - shared footprint family) | BGA (PEX88000 family - larger ball array) |
| Brand | Broadcom | Broadcom | Broadcom |
| Process Technology | CMOS | CMOS | CMOS |
| Hot-Plug Support | Yes | Yes | Yes |
| SR-IOV Support | Yes | Yes | Yes |
Key Differentiators
- 32-lane mid-range density sweet spot for mainstream server backplanes (vs PEX88096B0-DB)
- Mature Broadcom PEX88000 family firmware ecosystem (vs SS05-0B00-00)
- 70 C maximum operating temperature supports edge-server thermal envelopes (vs Industrial-grade PCIe switches (extended temp))
Design Notes
The SS06-0B00-00 BGA package requires length-matched differential pairs for every PCIe lane. According to Broadcom PEX88000 reference design guidance, TX/RX intra-pair skew must be held below 5 ps and inter-pair skew below 30 ps to meet PCIe CEM tolerances. Use a continuous reference ground plane under the BGA, and avoid routing signals across the BGA's power-plane void.
Estimated: typical supply rails for the SS06-0B00-00 include a 0.9 V core rail and a 1.8 V IO rail, with bulk decoupling of at least 22 uF ceramic plus 100 nF high-frequency bypass per power pin. Confirm exact rail count and tolerance against the manufacturer datasheet before committing the PCB stack-up. Inadequate decoupling is the most common root cause of PCIe link-training instability.
Do not reuse firmware images across SS06-0B00-00 SKUs in the PEX88000 family without re-validating port configuration. The SS05-0B00-00 and PEX88096B0-DB have different lane counts and default bifurcation settings; loading the wrong firmware can lock up the switch. Always load firmware from the external SPI flash and verify the checksum before link training.
Compliance Information
RoHS and REACH compliance inferred from Broadcom's standard product environmental policy; not explicitly stated in the verified distributor listings. AEC-Q100 not applicable (server/storage IC).
