SS05-0B00-00 - PEX88048 PCIe Gen5 Switch IC | Broadcom
MPN: SS05-0B00-00 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
SS05-0B00-00 Overview
A PCI Express switch is a high-speed serial interconnect device that fans out a single PCIe upstream port to multiple downstream endpoints, enabling point-to-point topologies beyond the limits of a single root complex or endpoint. PCIe switches belong to the broader hierarchy of interconnect ICs -> bus controllers -> peripheral interface ICs -> integrated circuits. Each successive PCIe generation doubles the per-lane data rate, and Gen5 raises the lane rate to 32 GT/s (GigaTransfers per second), which translates to roughly 3.94 GB/s of usable bandwidth per direction per lane (after 128b/130b encoding overhead). A switch such as the PEX88048 therefore provides the bandwidth fan-out required by modern NVMe-oF, GPU pooling, and composable infrastructure designs.
Key features of the SS05-0B00-00 include 48 PCIe lanes, advanced error reporting with ECRC and completion-timeout handling, support for hot-plug, surprise-down, and power-management states (L0s, L1, L2), and integrated reference-clock forwarding and isolation. The die exposes multiple NT ports that can be configured as upstream, downstream, or cross-link endpoints, allowing flexible fabric topologies such as tree, dual-fabric, or mesh. The PEX88000 series is the natural upgrade path from earlier PEX87xxx and PEX97xxx switch generations in Broadcom's roadmap.
Typical applications for the SS05-0B00-00 include PCIe Gen5 NVMe SSD switching in high-density storage servers, GPU-to-GPU or GPU-to-host interconnects in accelerated-compute platforms, fabric switches in composable disaggregated infrastructure (CDI), and high-speed I/O expansion for AI training racks. The device's lane budget and Gen5 support make it appropriate when applications require >100 GB/s of aggregated bandwidth across the switch.
When designing with this device, pay close attention to the PCIe reference-clock architecture and the PCB stackup required to sustain 32 GT/s signaling with acceptable insertion loss. Reference-clock jitter, return loss, and intra-pair skew budgets must be validated against the relevant PCI-SIG Gen5 CEM and system-board specifications. Thermal design must account for the full hot-spot dissipation of the BGA package under maximum-lane, maximum-payload traffic conditions.
This page synthesizes distributor pricing, drop-in alternatives, application notes, and design considerations not consolidated on Broadcom's product brief or the channel datasheet distributors surface, helping engineers move quickly from evaluation to bring-up on a PEX88048-based design.
Drop-in alternatives for SS05-0B00-00 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SS05-0B00-00 (same form factor and footprint) — differing in RoHS Status, Hot-Plug Support, Management Interface, PCIe Generation, Package Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PEX88096B0-DB
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$1145 / Unit
View Datasheet →PEX88032B0-DB
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SS05-0B00-00 Maximum Ratings & Electrical Characteristics
| Product Type | PCI Express (PCIe) Switch IC |
| Series | PEX88000 |
| Underlying Die / Variant | PEX88048B0-DB |
| PCIe Generation | PCIe Gen5 (32 GT/s per lane, per distributor datasheet classification) |
| PCIe Lanes | 48 |
| Switch Topology | Multi-port NT (configurable upstream/downstream/cross-link) |
| Maximum Lane Rate | 32 GT/s (PCIe Gen5) |
| Operating Temperature Range | 0 C to +70 C (commercial) |
| Package Type | BGA (surface-mount) |
| Mounting Type | Surface Mount |
| Packaging Media | Tray |
| Sub-Category | Interface - Analog Switches - Special Purpose (per Octopart classification) |
| Features | PCI Express Switch IC Channel |
| RoHS Status | Compliant (per distributor listing) |
| Family | SS05-0B00-00 / PEX88000 family |
SS05-0B00-00 bga (surface-mount) Pin Configuration Guide
Pin configuration for SS05-0B00-00 (bga (surface-mount) package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for SS05-0B00-00.
Refer to the datasheet for full pin configuration.
Typical Applications
SS05-0B00-00 is suitable for 6 applications: PCIe Gen5 NVMe Storage Fabric, GPU / AI Accelerator Fabric, Composable Disaggregated Infrastructure (CDI) Switch, PCIe Gen5 I/O Expansion / IOV, Data Center Accelerator Pooling, High-Performance NVMe-oF / Storage Class Memory.
PCIe Gen5 NVMe Storage Fabric
The SS05-0B00-00 (PEX88048B0-DB) is a strong fit for PCIe Gen5 NVMe fan-out in high-density storage servers because its 48 Gen5 lanes (>180 GB/s aggregate) outpace Gen4 alternatives per lane. Placed downstream of a root complex, it fans out an x16 Gen5 upstream port into multiple x4 / x8 Gen5 downstream ports feeding NVMe SSDs. Designers validate hot-plug, surprise-down, and thermal envelopes against the PEX88000 datasheet before signing off.
Recommended
GPU / AI Accelerator Fabric
Used as a fan-out switch in GPU training racks, the SS05-0B00-00 supplies the Gen5 lane budget and NT-port flexibility required to feed 8+ accelerators with peer-to-peer bandwidth. Compared with Gen4 designs, the 32 GT/s line rate reduces link-count overhead and keeps collective-comms latency budgets within reach. System architects pair it with retimer/redriver parts and validate Gen5 CEM compliance pre-tapeout.
Recommended
Composable Disaggregated Infrastructure (CDI) Switch
The SS05-0B00-00 fits the role of fabric switch inside composable disaggregated infrastructure racks, where compute, storage, and memory resources are pooled over PCIe. Its Gen5 line rate and NT-port flexibility make it ideal for tree / dual-fabric topologies that connect pooled resources on demand. Operating-temperature, hot-plug, and surprise-down support are validated against the PEX88000 datasheet for production release.
Recommended
PCIe Gen5 I/O Expansion / IOV
In hyperscale servers, the SS05-0B00-00 provides PCIe Gen5 expansion ports for accelerator cards, NICs, and CXL-style devices. Compared to a Gen4 PEX87xxx design, it allows more lanes at higher line rates per slot, reducing slot count and BOM. Single-root I/O virtualization (SR-IOV) personalities and VF arbitration must be validated per the PEX88000 datasheet.
Recommended
Data Center Accelerator Pooling
Within an accelerator-pooling chassis, the SS05-0B00-00 acts as the Gen5 fabric switch that connects pooled GPUs or FPGAs to host servers at x16 Gen5 per link. The 48-lane budget supports several pooled accelerators across multiple hosts, enabling resource sharing without over-subscription. Validate PCIe Gen5 link-training, equalization, and receiver margins against the PEX88000 datasheet before sign-off.
Recommended
High-Performance NVMe-oF / Storage Class Memory
Storage-class memory fabrics over NVMe-oF rely on the SS05-0B00-00 to maintain low-latency, high-bandwidth PCIe tunnels between pooling appliances and host servers. The Gen5 line rate substantially raises per-cable bandwidth versus Gen4 NVMe-oF fabrics, reducing cable or fiber count per appliance. Confirm NVMe-oF controller alignment, support for surprise-removal events, and platform power management states against the PEX88000 datasheet.
Recommended
Recommended Products Summary
Engineering reference data for SS05-0B00-00 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PEX88096B0-DB | PEX88032B0-DB |
|---|---|---|---|
| Brand | Broadcom | Broadcom | Broadcom |
| Package | BGA (PEX88000 family) | BGA (PEX88000 family) | BGA (PEX88000 family) |
| PCIe Generation | Gen5 (32 GT/s) | Gen5 (32 GT/s) | Gen5 (32 GT/s) |
| PCIe Lanes | 48 | 96 (double the lanes of SS05-0B00-00) | 32 (-33% vs SS05-0B00-00) |
| Switch Architecture | PEX88048B0-DB, NT-port configurable | PEX88096B0, NT-port configurable | PEX88032B0, NT-port configurable |
| Operating Temperature Range | 0 C to +70 C | 0 C to +70 C (commercial family) | 0 C to +70 C (commercial family) |
| Packaging Media | Tray | Tray (PEX88000 family) | Tray (PEX88000 family) |
| Sub-Category | Interface - Analog Switch - Special Purpose (PCIe Switch) | Interface - PCIe Switch | Interface - PCIe Switch |
| Param Match (this MPN -> alternative) | 100% (reference) | 90% (lane upgrade, same family) | 70% (lane reduction, same family) |
Key Differentiators
- 48-lane Gen5 PCIe switch built on PEX88048B0 silicon (vs PEX88032B0-DB)
- Right-sized lane count for mainstream Gen5 fan-out (vs PEX88096B0-DB)
- Same PEX88000 register interface for software reuse (vs Earlier PEX87xxx or PEX97xxx Gen4/Gen3 PCIe switches)
- BGA surface-mount package suited to high-density server PCBs (vs Generic BGA non-Broadcom PCIe switches)
Design Notes
Estimated: PCIe Gen5 signals at 32 GT/s are far more loss-sensitive than Gen4. Hold intra-pair skew below 5 ps, keep the differential reference-clock trace matched to within 100 um, and isolate the 100 MHz RefClk+ from noisy DC-DC regions with a guard trace. Use the PEX88000 datasheet's IBIS-AMI models during pre-layout channel analysis to avoid post-tape-out surprises; Gen5 retimer/redriver parts often must be inserted on long server-board traces.
Estimated: BGA power dissipation scales with lane count and payload utilization, and the SS05-0B00-00's BGA package has a thermal resistance profile that should be derived from the datasheet, not estimated. Build airflow margins for 70 C intake and provide a thermal relief pattern under the BGA to keep case temperature within the 0 C to +70 C commercial envelope under maximum Gen5 traffic. Heatsink attachment must avoid warpage that could breach BGA solder joints.
A common mistake is treating any 'PCIe switch' as pin-compatible across generations; the SS05-0B00-00 is only compatible with other PEX88000-family members in electrical and register terms. Another is omitting the sideband PERST#, REFCLK+, and sideband PERn0/PERp0 routing; missing sideband links cause link-training failures. Reference the manufacturer's reference schematic and follow the PERn/PERp pairing rules documented in the PEX88000 datasheet.
Estimated: a Gen5 PCIe switch can pull significant supply current in bursts during link-training, so bulk decoupling must be co-designed with the DC-DC regulator. Isolate PEX main rails from surrounding noisy rails with a ferrite + bulk cap bank, and respect the soft-start and ramp sequencing required by the PEX88000 datasheet. Hot-swap / hot-plug cabling should use inrush-limiting and pre-charge to avoid simultaneous hot-plug events triggering OVP.
Run a 3D EM simulation of the BGA breakout before tape-out: Gen5 PCB loss targets are typically < -1 dB/in at 16 GHz for the longest routes, and the BGA via field can dominate impedance if not co-designed with your stackup. Maintain a continuous reference plane beneath the PEX88048 lane traces and avoid splitting the plane under high-speed diffpairs. Validate S-parameter sweeps against Gen5 channel margin rather than Gen4 specifications.
Compliance Information
RoHS compliance surfaced by distributor listing; REACH, lead-free finish, halogen-free status, and full conflict-minerals declarations must be requested directly from Broadcom as a compliance certificate for qualification.
