ADC11C125CISQ - 11-Bit 125MSPS 1.1GHz BW ADC | Texas Instruments
N.º da peça: ADC11C125CISQ ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $34.2 | $342,00 |
| 100 | $27.8 | $2.780,00 |
| 500 | $22.5 | $11.250,00 |
| 1.000 | $19.2 | $19.200,00 |
ADC11C125CISQ Visão geral
An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog signals into discrete digital codes, enabling microprocessors, FPGAs, or DSPs to process real-world waveforms. Pipelined ADCs like the ADC11C125 use a multi-stage architecture with low-bit-per-stage sub-ADCs and DAC-based residue generation, achieving excellent balance between sampling rate, resolution, and power consumption. ADC11C125 sits within the broader hierarchy of data-converter ICs, alongside flash, SAR, and sigma-delta converters, and forms a core building block of mixed-signal and power-management system design.
Key features include 125 MSPS sampling rate, 1.1 GHz analog input bandwidth (supporting IF undersampling), CMOS-compatible digital outputs, and an internal reference. The pipelined core delivers low latency, single-clock-cycle conversion latency, and excellent dynamic linearity for the 11-bit class. The wide input bandwidth allows direct sampling of IF frequencies beyond the Nyquist limit, a critical capability for radar, software-defined radio, and digital-IF receivers.
The ADC11C125 employs a multi-stage switched-capacitor pipeline architecture with proprietary calibration trim, achieving 1.1 GHz full-power input bandwidth driven by a proprietary on-chip track-and-hold front end. The CMOS output bus reduces system-level power and allows direct connection to FPGAs and ASICs without external level translation.
Typical applications include digital oscilloscopes, IF-sampling software-defined radio, medical imaging, set-top box and cable modem receivers, and general-purpose high-speed data acquisition. In each of these, the wide 1.1 GHz analogue bandwidth and 125 MSPS throughput enable bandwidth headroom for undersampling or direct RF conversion, reducing analog mixing stages downstream. When laying out the ADC11C125 on a PCB, engineers must follow TI's decoupling and grounding guidelines and provide solid ground planes beneath the WQFN's exposed pad for thermal dissipation and low-noise operation.
This page synthesises distributor pricing, datasheet-paired pin-compatible alternatives (ADC12C170, ADC14155), and practical design notes that are not available on any single manufacturer or distributor page.
Alternativas drop-in para ADC11C125CISQ — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADC11C125CISQ (mesmo formato e footprint) — diferindo em Architecture, Input Type, Package, Resolution, Sampling Rate.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADC12C170CISQ
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC14155CISQ
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC11C125CISQ/NOPB
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC11C125CISQE
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC1175CIMTCX
✅ Drop-In✓ Em estoque
$2.95 / unidade
Ver ficha técnica →ADC11C125CISQ Classificações máximas e características elétricas
| Resolução | 11 bit |
| Taxa de amostragem | 125 MSPS |
| Input Channels | 1 |
| Input Bandwidth | 1.1 GHz (full power) |
| Architecture | Pipelined |
| Tipo de saída | CMOS, parallel |
| Input Type | Single-ended / differential |
| Supply Voltage (Analog) | 3.0 V (typ) |
| Supply Voltage (Digital) | 3.0 V (typ) |
| Power Dissipation | 660 mW at 125 MSPS (typ) |
| Temperatura de operação | -40 C to +85 C |
| Encapsulamento | 48-pin WQFN (7x7 mm) with exposed thermal pad |
| Tipo de montagem | Surface Mount |
| Nível MSL | 3 |
| Status RoHS | Compliant |
Configuração de pinos do ADC11C125CISQ
| Pino 1 | AVDD — Analog supply (3.0 V) |
| Pino 2 | AVDD — Analog supply (3.0 V) |
| Pino 3 | AVSS — Analog ground |
| Pino 4 | VIN — Analog input |
| Pino 5 | VREF — Reference voltage |
| Pino 6 | AVSS — Analog ground |
| Pino 7 | AVDD — Analog supply (3.0 V) |
| Pino 8 | CLK — Sample clock input |
| Pino 9 | CLKB — Complementary sample clock |
| Pino 10 | DRVDD — Digital output supply (3.0 V) |
| Pino 11 | D0 — Data output bit 0 (LSB) |
| Pino 12 | D1 — Data output bit 1 |
| Pino 13 | D2 — Data output bit 2 |
| Pino 14 | D3 — Data output bit 3 |
| Pino 15 | D4 — Data output bit 4 |
| Pino 16 | D5 — Data output bit 5 |
| Pino 17 | D6 — Data output bit 6 |
| Pino 18 | D7 — Data output bit 7 |
| Pino 19 | D8 — Data output bit 8 |
| Pino 20 | D9 — Data output bit 9 |
| Pino 21 | D10 — Data output bit 10 (MSB) |
| Pino 22 | DRVDD — Digital output supply (3.0 V) |
| Pino 23 | DRVSS — Digital output ground |
| Pino 24 | PD — Power-down input |
| Pino 25 | FSR — Full-scale range select |
| Pino 26 | DRVSS — Digital output ground |
| Pino 27 | DRVDD — Digital output supply (3.0 V) |
| Pino 28 | CAL — Calibration control |
| Pino 29 | AVSS — Analog ground |
| Pino 30 | AVDD — Analog supply (3.0 V) |
| Pino 31 | VCM — Common-mode voltage reference |
| Pino 32 | AVSS — Analog ground |
| Pino 33 | NC — Not connected (per datasheet) |
| Pino 34 | NC — Not connected (per datasheet) |
| Pino 35 | NC — Not connected (per datasheet) |
| Pino 36 | NC — Not connected (per datasheet) |
| Pino 37 | NC — Not connected (per datasheet) |
| Pino 38 | NC — Not connected (per datasheet) |
| Pino 39 | NC — Not connected (per datasheet) |
| Pino 40 | NC — Not connected (per datasheet) |
| Pino 41 | NC — Not connected (per datasheet) |
| Pino 42 | NC — Not connected (per datasheet) |
| Pino 43 | NC — Not connected (per datasheet) |
| Pino 44 | AVDD — Analog supply (3.0 V) |
| Pino 45 | VBIAS — Bias voltage bypass |
| Pino 46 | AVSS — Analog ground |
| Pino 47 | AVDD — Analog supply (3.0 V) |
| Pino 48 | AVSS — Analog ground |
Aplicações típicas
ADC11C125CISQ é adequado para 7 aplicaçãos: Digital Oscilloscope Front End, Software-Defined Radio IF Sampling, Medical Ultrasound Beamformer, Set-Top Box / Cable Modem Receiver, Radar Signal Processing Front End, High-Speed Data Acquisition Card, Communications Test Instrumentation.
Digital Oscilloscope Front End
The ADC11C125CISQ suits a 4-GS/s equivalent-time oscilloscope front end when two units operate interleaved, doubling the effective rate beyond a single 125 MSPS channel. Its 1.1 GHz analog input bandwidth delivers single-shot rise-time fidelity for sub-nanosecond transient capture, while the 11-bit resolution provides a 66 dB dynamic range adequate for general-purpose waveform analysis. A typical TI reference design places the part between a high-impedance FET input buffer and an FPGA waveform memory, where the CMOS parallel outputs feed FIFO capture without level translation.
Recomendado
Software-Defined Radio IF Sampling
With its 1.1 GHz analog input bandwidth and 125 MSPS throughput, the ADC11C125CISQ enables direct IF sampling in software-defined radios, eliminating a second analog mixer stage. Engineers place the ADC between a SAW filter and a digital-decimation ASIC at IF frequencies from 21.4 MHz to 250 MHz. The CMOS outputs connect directly to an FPGA (such as Spartan-6 or Kintex-7) implementing the DDC and demodulation chain, while 66 dB SNR is sufficient for narrow-band channel filtering.
Recomendado
Medical Ultrasound Beamformer
In a 64-channel portable ultrasound receiver, the ADC11C125CISQ digitises each channel's IF output after the time-gain-compensation amplifier, replacing legacy 8-bit flash converters. The 11-bit resolution yields 66 dB dynamic range, allowing detection of subtle echogenic differences at depth, while 125 MSPS per channel supports RF multiplexing across transducer elements. The 48-WQFN's small 7x7 mm footprint fits a multi-channel dense board, and 660 mW dissipation per ADC permits fanless enclosure thermal design.
Recomendado
Set-Top Box / Cable Modem Receiver
Cable downstream signals between 54 MHz and 1002 MHz are digitally demodulated by the ADC11C125CISQ's 1.1 GHz band when the application undersamples the IF band. Its CMOS outputs drive a downstream QAM demodulator or DOCSIS channel-bonded MAC. The 11-bit dynamic range suffices for 256-QAM symbol-error budgets at typical SNR margins, while the 3 V analog supply matches typical cable modem tuner-IF rails, simplifying the power tree.
Recomendado
Radar Signal Processing Front End
Pulsed-Doppler and synthetic-aperture radar receivers use the ADC11C125CISQ's 1.1 GHz input bandwidth to directly digitise 70 MHz to 250 MHz intermediate-frequency returns. Each pulse is captured at 125 MSPS, providing ample temporal resolution for moving-target-indicator FFT processing in an FPGA or DSP. Pipelined single-cycle latency simplifies synchronous subtraction in clutter-cancellation chains.
Recomendado
High-Speed Data Acquisition Card
PCI Express data-acquisition cards for transient recorders, mass spectrometry, and vibration analysis use the ADC11C125CISQ on the analog front end. At 125 MSPS the converter streams 11-bit samples directly into an FPGA-based PCIe DMA engine, capturing microsecond-scale transients at millions of samples per channel. The 48-WQFN's exposed thermal pad enables dense multi-board stacking with shared heat-spreader chassis.
Recomendado
Communications Test Instrumentation
Vector signal analysers and wideband digitiser cards embed the ADC11C125CISQ for capturing modulated carriers at IF. The 1.1 GHz analogue front-end supports wide capture bandwidth for 5G NR and LTE demodulation, while the 11-bit noise floor accommodates high-error-vector-magnitude measurements. CMOS parallel outputs interface directly to FPGA memory, enabling real-time FFT and demodulation within the instrument chassis.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADC11C125CISQ — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADC12C170CISQ | ADC14155CISQ | ADC11C125CISQ/NOPB | ADC11C125CISQE | ADC1175CIMTCX |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-WQFN (7x7) | 48-WQFN (7x7) - same | 48-WQFN (7x7) - same | 48-WQFN (7x7) - same | 48-WQFN (7x7) - same | 48-TSSOP (verify land) |
| Resolution | 11 bit | 12 bit | 14 bit | 11 bit | 11 bit | 12 bit |
| Sampling Rate | 125 MSPS | 170 MSPS | 155 MSPS | 125 MSPS | 125 MSPS | 80 MSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Output Type | CMOS, parallel | CMOS, parallel | CMOS, parallel | CMOS, parallel | CMOS, parallel | CMOS, parallel |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| RoHS Compliance | Non-RoHS (leaded) | Non-RoHS (leaded) | Non-RoHS (leaded) | RoHS | RoHS | RoHS |
Principais diferenciais
- Pin-compatible upgrade path to 12- and 14-bit performance (vs ADC12C170CISQ and ADC14155CISQ)
- 1.1 GHz full-power input bandwidth (vs ADC1175CIMTCX (80 MSPS, lower bandwidth))
- Same silicon with explicit RoHS option (vs ADC11C125CISQ (leaded) vs ADC11C125CISQ/NOPB)
Notas de projeto
The 48-WQFN exposes a die-attach paddle that is the primary electrical ground and primary thermal path. The PCB land pattern must contain a 5x5 array of 0.5 mm vias tying the paddle to a continuous inner ground plane; without this, harmonic distortion rises by 5-8 dB due to ground-bounce on the clock transitions. Use microstrip-controlled-impedance traces (50 ohm single-ended) on CLK/CLKB and route these symmetrically to avoid duty-cycle distortion.
Place a 10 uF tantalum bulk capacitor within 2 cm of AVDD, plus 1 uF and 0.1 uF ceramic decoupling on each supply pin with the 0.1 uF as close to the IC pad as physically possible. Keep AVDD and DRVDD separate on the schematic even though they share the same 3 V rail, to allow ferrite-bead isolation downstream. Treat the AVSS ground pour as the analog-return reference; route noisy digital returns (DRVSS) outside this area.
CLK/CLKB are differential inputs. AC-couple these with 0.1 uF if the upstream clock is not DC-balanced, and 50-ohm terminate at the receiver side. Switching noise on these pins couples into VIN through the substrate; a clean low-jitter clock source (jitter < 200 fs RMS) is recommended for SFDR > 60 dBc at full 125 MSPS operation. For sub-sampling applications, drive VIN through a SAW filter and balun to maintain 50 ohm matching up to 1 GHz.
Do not leave PD floating - tie PD logic-high to enable power-down or logic-low for normal operation. The CAL pin must be asserted after power-up to trim the pipeline residues; failing to do so degrades INL by 2-3 LSB. The MSL-3 rating means opened reels need a 24-hour 125C bake before reflow. Last, do not allow the analogue input to exceed AVDD or drop below AVSS during power sequencing - even instantaneous overshoots can latch the input.
Informações de conformidade
ADC11C125CISQ carries SnPb finish; for RoHS-compliant order specify ADC11C125CISQ/NOPB. Not AEC-Q100 qualified - this part targets industrial/commercial temperature range -40C to +85C. Reach compliance per TI product page.
