EPM7128ELC84-20 - MAX 7000 CPLD, 128MC, 20ns, 5V, PLCC-84 | Altera
N.º da peça: EPM7128ELC84-20 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $42.7 | $42,70 |
| 10 | $38.5 | $385,00 |
| 100 | $32.1 | $3.210,00 |
| 500 | $27.85 | $13.925,00 |
| 1.000 | $24.2 | $24.200,00 |
EPM7128ELC84-20 Visão geral
What is a CPLD? A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs (such as PALs and GALs) and FPGAs in the programmable logic hierarchy. CPLDs are characterized by instant-on (no configuration load time), deterministic timing, and low power consumption, making them ideal for glue-logic, bus interfacing, and state-machine tasks. The MAX 7000 family is based on Altera's second-generation MAX architecture and supports 100% TTL emulation while integrating SSI, MSI, and LSI logic functions on a single device.
Key features of the EPM7128ELC84-20 include 5V core operation, 2500 typical gates (the -20 speed grade corresponds to a 20 ns tPD and approximately 125 MHz in-system performance), in-system programmability via the IEEE Std. 1149.1 (JTAG) interface, and four pin-compatible speed grades (-5, -7, -10, -12, -15, -20) that allow designers to migrate between speed and power trade-offs without PCB rework. The device is fabricated on an EEPROM-based process, providing non-volatile storage of the configuration so the part powers up instantly programmed.
Architecturally, the EPM7128ELC84-20 implements the Logic Array Blocks (LABs) connected through the Programmable Interconnect Array (PIA). Each macro cell contains a programmable AND/OR array with a flip-flop, shareable expanders, and a configurable I/O architecture supporting 3.3V or 5V interface levels. The 84-pin PLCC (J-Lead) package has a JEDEC MS-018 footprint and supports 68 user I/O with 4 dedicated inputs (GCLK, OE2/GCLK2, OE1, CLR) plus TDI, TDO, TMS, TCK for JTAG.
Typical applications include address decoding and bus-interface glue logic in 5V microprocessor systems, peripheral control in industrial automation, I/O expansion and signal conditioning in legacy telecom equipment, and prototyping platforms that benefit from instant-on programmable logic. Compared to FPGAs, the MAX 7000 family excels at deterministic combinatorial paths and is widely used in PC/104, ISA, and 8051-family bus arbiter designs.
When designing with this part, note that the PLCC-84 J-Lead package requires a through-hole or socket footprint, which makes field replacement easy. Designers should follow Altera's MAX 7000 family datasheet guidelines for power decoupling (typically 0.1 uF + 10 uF bulk near VCC pins) and unused-pin termination (tie unused I/Os to VCC or GND through 10 kohm to minimize quiescent current).
This page synthesizes distributor pricing, drop-in 5V same-package alternatives within the MAX 7000 family, and practical design notes not found in the manufacturer datasheet.
Alternativas drop-in para EPM7128ELC84-20 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM7128ELC84-20 (mesmo formato e footprint) — diferindo em Mounting Type, RoHS Status, Package, Family, Supply Voltage (VCCINT).
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM7128ELC84-15
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM7128ELC84-12
✅ Drop-In✓ Em estoque
$10.4 / unidade
Ver ficha técnica →EPM7128ELC84-10
✅ Drop-In✓ Em estoque
$7.2 / unidade
Ver ficha técnica →EPM7128AELC84-10N
✅ Drop-In✓ Em estoque
$10.45 / unidade
Ver ficha técnica →EPM7128ELI84-20
✅ Drop-In✓ Em estoque
$7.95 / unidade
Ver ficha técnica →EPM7128SLC84-6N
✅ Drop-In✓ Em estoque
$8.75 / unidade
Ver ficha técnica →EPM7128ELC84-20 Classificações máximas e características elétricas
| Series | MAX 7000 |
| Device Family | EPM7128 (CPLD) |
| Number of Macrocells | 128 |
| Number of Usable Gates | 2500 |
| Number of User I/Os | 68 |
| Number of Logic Array Blocks (LABs) | 8 |
| Propagation Delay (tPD) | 20 ns |
| Maximum Frequency (fCNT) | 62.5 MHz |
| Supply Voltage (VCC) | 5 V |
| Supply Voltage Tolerance | 4.75 V to 5.25 V |
| Technology | CMOS, EEPROM-based (non-volatile) |
| Programmable Interface | IEEE Std. 1149.1 (JTAG) |
| Package Type | PLCC-84 (J-Lead, J-bend) |
| Tipo de montagem | Surface Mount (PLCC socket compatible) |
| Temperatura de operação | 0C to +70C (commercial) |
| Status RoHS | Contains lead (pre-RoHS, SnPb finish) |
Configuração de pinos do EPM7128ELC84-20
| Pino 1 | I/O — User I/O (macrocell pin) |
| Pino 2 | I/O — User I/O (macrocell pin) |
| Pino 3 | I/O — User I/O (macrocell pin) |
| Pino 4 | I/O — User I/O (macrocell pin) |
| Pino 5 | I/O — User I/O (macrocell pin) |
| Pino 6 | I/O — User I/O (macrocell pin) |
| Pino 7 | I/O — User I/O (macrocell pin) |
| Pino 8 | I/O — User I/O (macrocell pin) |
| Pino 9 | I/O — User I/O (macrocell pin) |
| Pino 10 | I/O — User I/O (macrocell pin) |
| Pino 11 | I/O — User I/O (macrocell pin) |
| Pino 12 | TDI — JTAG Test Data In |
| Pino 13 | I/O — User I/O (macrocell pin) |
| Pino 14 | I/O — User I/O (macrocell pin) |
| Pino 15 | VCC — 5V supply |
| Pino 16 | I/O — User I/O (macrocell pin) |
| Pino 17 | I/O — User I/O (macrocell pin) |
| Pino 18 | I/O — User I/O (macrocell pin) |
| Pino 19 | I/O — User I/O (macrocell pin) |
| Pino 20 | I/O — User I/O (macrocell pin) |
| Pino 21 | GND — Ground |
| Pino 22 | I/O — User I/O (macrocell pin) |
| Pino 23 | I/O — User I/O (macrocell pin) |
| Pino 24 | I/O — User I/O (macrocell pin) |
| Pino 25 | I/O — User I/O (macrocell pin) |
| Pino 26 | I/O — User I/O (macrocell pin) |
| Pino 27 | I/O — User I/O (macrocell pin) |
| Pino 28 | I/O — User I/O (macrocell pin) |
| Pino 29 | I/O — User I/O (macrocell pin) |
| Pino 30 | I/O — User I/O (macrocell pin) |
| Pino 31 | GND — Ground |
| Pino 32 | I/O — User I/O (macrocell pin) |
| Pino 33 | I/O — User I/O (macrocell pin) |
| Pino 34 | I/O — User I/O (macrocell pin) |
| Pino 35 | I/O — User I/O (macrocell pin) |
| Pino 36 | I/O — User I/O (macrocell pin) |
| Pino 37 | I/O — User I/O (macrocell pin) |
| Pino 38 | I/O — User I/O (macrocell pin) |
| Pino 39 | TMS — JTAG Test Mode Select |
| Pino 40 | VCC — 5V supply |
| Pino 41 | I/O — User I/O (macrocell pin) |
| Pino 42 | I/O — User I/O (macrocell pin) |
| Pino 43 | I/O — User I/O (macrocell pin) |
| Pino 44 | I/O — User I/O (macrocell pin) |
| Pino 45 | I/O — User I/O (macrocell pin) |
| Pino 46 | I/O — User I/O (macrocell pin) |
| Pino 47 | I/O — User I/O (macrocell pin) |
| Pino 48 | I/O — User I/O (macrocell pin) |
| Pino 49 | GND — Ground |
| Pino 50 | I/O — User I/O (macrocell pin) |
| Pino 51 | GCLK — Global Clock (dedicated input) |
| Pino 52 | OE2/GCLK2 — Global OE / Global Clock 2 (dedicated input) |
| Pino 53 | I/O — User I/O (macrocell pin) |
| Pino 54 | I/O — User I/O (macrocell pin) |
| Pino 55 | I/O — User I/O (macrocell pin) |
| Pino 56 | I/O — User I/O (macrocell pin) |
| Pino 57 | I/O — User I/O (macrocell pin) |
| Pino 58 | I/O — User I/O (macrocell pin) |
| Pino 59 | I/O — User I/O (macrocell pin) |
| Pino 60 | I/O — User I/O (macrocell pin) |
| Pino 61 | TCK — JTAG Test Clock (dedicated input) |
| Pino 62 | VCC — 5V supply |
| Pino 63 | I/O — User I/O (macrocell pin) |
| Pino 64 | I/O — User I/O (macrocell pin) |
| Pino 65 | I/O — User I/O (macrocell pin) |
| Pino 66 | I/O — User I/O (macrocell pin) |
| Pino 67 | I/O — User I/O (macrocell pin) |
| Pino 68 | I/O — User I/O (macrocell pin) |
| Pino 69 | I/O — User I/O (macrocell pin) |
| Pino 70 | I/O — User I/O (macrocell pin) |
| Pino 71 | GND — Ground |
| Pino 72 | I/O — User I/O (macrocell pin) |
| Pino 73 | I/O — User I/O (macrocell pin) |
| Pino 74 | OE1 — Global Output Enable 1 (dedicated input) |
| Pino 75 | I/O — User I/O (macrocell pin) |
| Pino 76 | I/O — User I/O (macrocell pin) |
| Pino 77 | I/O — User I/O (macrocell pin) |
| Pino 78 | I/O — User I/O (macrocell pin) |
| Pino 79 | I/O — User I/O (macrocell pin) |
| Pino 80 | I/O — User I/O (macrocell pin) |
| Pino 81 | TDO — JTAG Test Data Out |
| Pino 82 | VCC — 5V supply |
| Pino 83 | I/O — User I/O (macrocell pin) |
| Pino 84 | CLR — Global Clear (dedicated input) |
Aplicações típicas
EPM7128ELC84-20 é adequado para 6 aplicaçãos: Microprocessor Address Decoding & Glue Logic, Legacy Industrial Control & Automation, PC/104, ISA, and VME Bus Interface Cards, Telecom & Networking Backplane Glue, Prototyping & Educational Logic Development, Aerospace & Defense Avionics Interfaces.
Microprocessor Address Decoding & Glue Logic
The EPM7128ELC84-20 excels at address decoding and bus-interface glue logic in 5V microprocessor systems. Its 128 macro cells and 68 user I/Os are well-matched to combine multiple 74LS/74F-series decoders, latches, and arbiters into a single instant-on non-volatile device. With 20 ns tPD the part sits comfortably below the propagation budget of 8051, 80188, and 68k-era CPU buses running at 25 MHz. The 5V VCC and TTL-compatible I/O thresholds interface directly with 5V peripherals without level shifting, and the JTAG-supported in-system programmability allows late-stage PCB revisions without socket rework. Compared to discrete SSI/MSI logic, the CPLD reduces board area, lowers power via internal optimization, and provides documented timing that simplifies static-timing analysis.
Recomendado
Legacy Industrial Control & Automation
In legacy industrial control racks, the EPM7128ELC84-20 consolidates PLC-style state machines, encoder quadrature decoders, and PWM generators into a single 5V programmable device. Its instant-on EEPROM configuration means no boot PROM and no watchdog reset is needed after power cycling, which is critical for unattended factory floor installations. The PLCC-84 J-Lead package accepts standard industrial sockets, simplifying field replacement without desoldering. With 2500 usable gates the CPLD handles multi-axis motion control logic, I/O debouncing, and serial protocol framing (RS-232/485 glue) in one chip. Industrial designers should choose the EPM7128ELI84-20 industrial-temperature variant for -40C to +85C environments; it is pin-compatible and drop-in replaceable on the same PLCC-84 footprint.
Recomendado
PC/104, ISA, and VME Bus Interface Cards
PC/104, ISA, and VME expansion cards traditionally use CPLDs to implement bus arbitration, address mapping, and interrupt steering, and the EPM7128ELC84-20 was a popular choice for these applications. Its 5V TTL-compatible I/Os match the original ISA bus levels directly, and the 68 available user I/Os are sufficient for 16-bit data plus 24-bit address plus control-signal decoding in one device. The 20 ns tPD adds only 1 wait-state to 8 MHz ISA cycles and is adequate for 12 MHz designs. In-system JTAG programming allows the same card to be re-used across multiple SKUs by re-flashing the CPLD bitstream, reducing inventory cost. Designers migrating to PCI or PCIe must replace both connector and logic; the EPM7128 family is not suited to 3.3V/33 MHz PCI signaling.
Recomendado
Telecom & Networking Backplane Glue
The EPM7128ELC84-20 was widely used in telecom line cards and networking backplanes for protocol conversion, clock-domain crossing, and TDM bus multiplexing. Its 5V tolerant I/Os interface with E1/T1 line-interface units (LIUs) and legacy TTL backplane logic, while the 8 LABs allow independent clock-domain FIFOs and rate-adaptation state machines. The deterministic 20 ns tPD simplifies meeting the hold-time requirements of source-synchronous backplane buses such as H.110 (CT Bus). Designers building new designs should note that the MAX 7000 family lacks 3.3V I/O, so ATCA or AMC backplanes will require the EPM7128SLC84-6N (3.3V core) or migration to MAX II/MAX V families with multi-voltage I/O support.
Recomendado
Prototyping & Educational Logic Development
The EPM7128ELC84-20 is a staple of university digital-logic laboratories and hobbyist prototyping platforms because it provides enough macro cells (128) for full single-cycle RISC CPU cores, custom peripherals, and bus controllers while remaining instantly reprogrammable via inexpensive JTAG cables such as the Altera ByteBlaster. Its 5V supply eliminates level-shifting concerns when interfacing to legacy TTL lab equipment, and the PLCC-84 socket accepts standard 84-pin machine-tooled ZIF sockets for quick swap-out during lab sessions. The well-documented MAX 7000 family reference designs in the Altera University Program include UART cores, VGA controllers, and 7-segment display drivers that target this exact density. Educators should pair the EPM7128ELC84-20 with a stable 5V/1A linear regulator and 0.1 uF + 10 uF decoupling per VCC pin to ensure repeatable student results.
Recomendado
Aerospace & Defense Avionics Interfaces
The EPM7128ELC84-20 has historically been used in avionics LRUs (Line Replaceable Units) for ARINC 429, MIL-STD-1553, and discrete-signal interface glue because its deterministic timing, instant-on EEPROM, and wide operating temperature (when paired with the I-grade variant) suit DO-254 and MIL-HDBK-454 design flows. The 68 user I/Os multiplex the receive/transmit channels of up to 4 ARINC 429 buses with parity generation, while the 8 LABs implement channel-decoding state machines. The PLCC-84 socket allows field replacement at forward operating bases without specialized rework tools. New avionics designs targeting DO-254 DAL A/B should consider the B-grade processed EPM7128ELI84-20 with extended temperature and traceability documentation, which is pin-compatible on the same PLCC-84 footprint.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM7128ELC84-20 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM7128ELC84-15 | EPM7128ELC84-12 | EPM7128ELC84-10 | EPM7128AELC84-10N | EPM7128ELI84-20 | EPM7128SLC84-6N |
|---|---|---|---|---|---|---|---|
| Brand | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) |
| Package | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) |
| Supply Voltage (VCC) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 3.3 V |
| Propagation Delay (tPD) | 20 ns | 15 ns (-25%) | 12 ns (-40%) | 10 ns (-50%) | 10 ns (-50%) | 20 ns (0%) | 6 ns (-70%) |
| Maximum Frequency | 62.5 MHz | 83.3 MHz | 100 MHz | 125 MHz | 125 MHz | 62.5 MHz | 166.7 MHz |
| Number of Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Number of User I/Os | 68 | 68 | 68 | 68 | 68 | 68 | 68 |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C | 0C to +70C |
| RoHS Compliance | No (SnPb finish) | No (SnPb finish) | No (SnPb finish) | No (SnPb finish) | Yes (lead-free) | No (SnPb finish) | No (SnPb finish) |
Principais diferenciais
- Slowest speed grade (-20) at lowest price point in MAX 7000 family (vs EPM7128ELC84-15)
- Drop-in industrial-temperature upgrade available (vs EPM7128ELI84-20)
- 5V core matches legacy TTL systems directly (vs EPM7128SLC84-6N)
Notas de projeto
The EPM7128ELC84-20 has multiple VCC pins (PLCC-84 pins 15, 40, 62, 82) that must each be decoupled with a 0.1 uF ceramic capacitor placed within 5 mm of the pin. Add a single bulk 10 uF tantalum or aluminum-polymer capacitor per VCC group to suppress switching transients during simultaneous-output switching (SSO). The I-grade variant draws similar quiescent current but extended temperature may increase I/O leakage; budget 50 mA typical ICC at full toggle.
The PLCC-84 J-Lead package (JEDEC MS-018) requires a 1.27 mm pitch land pattern with chamfered pin-1 indicator. For prototype work, install a through-hole PLCC socket (e.g., 3M 84-pin machined-pin socket) so the device can be swapped without desoldering - critical when working with obsolete parts where replacement stock may be limited. Production boards may solder the PLCC directly, but plan for a 1.5 mm keepout under the package body for cleaning and inspection.
Three pitfalls are commonly missed in MAX 7000 designs: (1) Unused I/O pins must be tied to GND through 10 kohm (or driven as outputs) to avoid floating-input quiescent-current spikes - leaving them open can add several mA of Icc. (2) The JTAG chain TDI->TDO order must match the BSDL file; reversing TDI/TDO causes programming failure but the device still functions normally. (3) The MAX 7000 family is 5V-only on the E-suffix parts - mixing 3.3V peripherals on the I/O bank requires the EPM7128SLC variant instead; do not exceed 5.25 V on VCC.
Informações de conformidade
EPM7128ELC84-20 is a pre-RoHS part with SnPb finish on PLCC-84 leads; REACH compliance unknown per Intel/Altera product page. For RoHS-compliant equivalents choose EPM7128AELC84-10N in the same PLCC-84 footprint.
