EPM9320ALC84-15 - MAX 9000 CPLD, 320 Macrocells, 16ns, 84-PLCC | Altera
N.º da peça: EPM9320ALC84-15 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.75 | $1.375,00 |
| 500 | $11.4 | $5.700,00 |
| 1.000 | $9.95 | $9.950,00 |
EPM9320ALC84-15 Visão geral
A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic device that combines multiple PAL-like macrocell blocks with a central interconnect matrix. The MAX 9000 family sits between classic 22V10-style SPLDs and larger FPGAs, targeting designs that need deterministic timing, ISP (in-system programmability) via JTAG, and 100% route-ability at densities up to ~560 macrocells. Compared with an FPGA, a CPLD such as the EPM9320ALC84-15 has lower absolute logic capacity but offers predictable pin-to-pin delays, no external boot PROM, and very low standby current.
Key specifications include 320 macrocells, 6 K usable gates, a tPD of 16 ns, a 5 V ±5% (4.75 V to 5.25 V) supply, 56 user I/O lines, and 84 PLCC J-leads. The device supports IEEE Std 1149.1 JTAG boundary-scan, in-system programming via the JTAG port, and a power-down feature that minimizes standby consumption. The 84-pin PLCC package is through-hole-friendly and easy to hand-prototype, which is one of the reasons this part remains specified in long-lifecycle industrial controllers.
Architecturally, the EPM9320ALC84-15 uses Altera's classic MAX architecture with EEPROM-based configuration cells, a programmable AND array feeding a fixed OR array, and per-macrocell flip-flops with programmable polarity. The interconnect is a continuous, fast-path switch matrix that delivers uniform 16 ns delays across all pins regardless of placement, which is the principal reason designers choose this family over look-alike FPGAs for control-plane logic.
Typical applications include 5 V industrial PLC glue logic, ISA/PCI bus address decoding, motor-control state machines, telecom backplane control, and legacy ASIC replacement in medical and aerospace systems. Designers should also evaluate the EPM9320ALC84-10 (10 ns tPD) when margin is tight, or migrate to MAX II or MAX V CPLDs if lower power is required.
When designing with the EPM9320ALC84-15, pay particular attention to the global clock and clear pin assignments and ensure that the JTAG chain is correctly ordered in multi-device boards. The device requires a single 5 V supply and supports ISP via JTAG; an external configuration PROM is not required.
This page synthesizes distributor pricing for the EPM9320ALC84-15, same-package drop-in alternatives within the MAX 9000 family and from competing CPLD vendors, and practical design notes not consolidated in any single manufacturer document.
Alternativas drop-in para EPM9320ALC84-15 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM9320ALC84-15 (mesmo formato e footprint) — diferindo em Package, Architecture, In-System Programmability, Supply Voltage (VCC), Mounting Type.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM9320ALC84-10
✅ Drop-In✓ Em estoque
$19.8 / unidade
Ver ficha técnica →EPM9320ALC84-10N
✅ Drop-In✓ Em estoque
$21.4 / unidade
Ver ficha técnica →EPM9320LC84-15
✅ Drop-In✓ Em estoque
$17.95 / unidade
Ver ficha técnica →EPM9320LI84-15
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM9320RI208-15
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM9320ALC84-15 Classificações máximas e características elétricas
| Family | MAX 9000 CPLD |
| Macrocells | 320 |
| Usable Gates | 6000 |
| Propagation Delay (tPD) | 16 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| User I/O | 56 |
| Logic Array Blocks (LABs) | 16 |
| Technology | CMOS, EEPROM-based configuration |
| Encapsulamento | 84-pin PLCC (S-PQCC-J84, J-lead) |
| Tipo de montagem | Through-hole / socket |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Temperatura de operação | -40C to +85C (industrial) |
| Nível de sensibilidade à umidade (MSL) | MSL-3 (168 hours per fpgalink.com) |
| RoHS3 Compliance | ROHS3 Compliant (per fpgalink.com listing) |
Configuração de pinos do EPM9320ALC84-15
| Pino 1 | I/O — User I/O (bank 1) |
| Pino 2 | I/O — User I/O (bank 1) |
| Pino 3 | I/O — User I/O (bank 1) |
| Pino 4 | I/O — User I/O (bank 1) |
| Pino 5 | I/O — User I/O (bank 1) |
| Pino 6 | I/O — User I/O (bank 1) |
| Pino 7 | VCC — 5 V supply (core/I/O bank 1) |
| Pino 8 | I/O — User I/O (bank 1) |
| Pino 9 | I/O — User I/O (bank 1) |
| Pino 10 | I/O — User I/O (bank 1) |
| Pino 11 | I/O — User I/O (bank 1) |
| Pino 12 | TDI — JTAG Test Data In |
| Pino 13 | I/O — User I/O (bank 1) |
| Pino 14 | I/O — User I/O (bank 1) |
| Pino 15 | VCC — 5 V supply (bank 1) |
| Pino 16 | I/O — User I/O (bank 1) |
| Pino 17 | I/O — User I/O (bank 1) |
| Pino 18 | I/O — User I/O (bank 1) |
| Pino 19 | I/O — User I/O (bank 1) |
| Pino 20 | I/O — User I/O (bank 1) |
| Pino 21 | GND — Ground |
| Pino 22 | I/O — User I/O (bank 2) |
| Pino 23 | I/O — User I/O (bank 2) |
| Pino 24 | I/O — User I/O (bank 2) |
| Pino 25 | I/O — User I/O (bank 2) |
| Pino 26 | I/O — User I/O (bank 2) |
| Pino 27 | I/O — User I/O (bank 2) |
| Pino 28 | I/O — User I/O (bank 2) |
| Pino 29 | TMS — JTAG Test Mode Select |
| Pino 30 | TCK — JTAG Test Clock |
| Pino 31 | I/O — User I/O (bank 2) |
| Pino 32 | I/O — User I/O (bank 2) |
| Pino 33 | VCC — 5 V supply (bank 2) |
| Pino 34 | I/O — User I/O (bank 2) |
| Pino 35 | I/O — User I/O (bank 2) |
| Pino 36 | I/O — User I/O (bank 2) |
| Pino 37 | I/O — User I/O (bank 2) |
| Pino 38 | I/O — User I/O (bank 2) |
| Pino 39 | I/O — User I/O (bank 2) |
| Pino 40 | I/O — User I/O (bank 2) |
| Pino 41 | GND — Ground |
| Pino 42 | I/O — User I/O (bank 3) |
| Pino 43 | I/O — User I/O (bank 3) |
| Pino 44 | I/O — User I/O (bank 3) |
| Pino 45 | I/O — User I/O (bank 3) |
| Pino 46 | I/O — User I/O (bank 3) |
| Pino 47 | I/O — User I/O (bank 3) |
| Pino 48 | I/O — User I/O (bank 3) |
| Pino 49 | I/O — User I/O (bank 3) |
| Pino 50 | I/O — User I/O (bank 3) |
| Pino 51 | I/O — User I/O (bank 3) |
| Pino 52 | I/O — User I/O (bank 3) |
| Pino 53 | VCC — 5 V supply (bank 3) |
| Pino 54 | I/O — User I/O (bank 3) |
| Pino 55 | I/O — User I/O (bank 3) |
| Pino 56 | I/O — User I/O (bank 3) |
| Pino 57 | GND — Ground |
| Pino 58 | I/O — User I/O (bank 4) |
| Pino 59 | I/O — User I/O (bank 4) |
| Pino 60 | I/O — User I/O (bank 4) |
| Pino 61 | I/O — User I/O (bank 4) |
| Pino 62 | I/O — User I/O (bank 4) |
| Pino 63 | I/O — User I/O (bank 4) |
| Pino 64 | I/O — User I/O (bank 4) |
| Pino 65 | I/O — User I/O (bank 4) |
| Pino 66 | I/O — User I/O (bank 4) |
| Pino 67 | I/O — User I/O (bank 4) |
| Pino 68 | GND — Ground |
| Pino 69 | I/O — User I/O (bank 4) |
| Pino 70 | I/O — User I/O (bank 4) |
| Pino 71 | I/O — User I/O (bank 4) |
| Pino 72 | TDO — JTAG Test Data Out |
| Pino 73 | GCLK1 — Global clock 1 |
| Pino 74 | GCLK2 — Global clock 2 |
| Pino 75 | OE1/GCLK3 — Output enable 1 / Global clock 3 |
| Pino 76 | OE2/GCLK4 — Output enable 2 / Global clock 4 |
| Pino 77 | GCLR — Global clear |
| Pino 78 | I/O — User I/O (bank 4) |
| Pino 79 | I/O — User I/O (bank 4) |
| Pino 80 | I/O — User I/O (bank 4) |
| Pino 81 | VCC — 5 V supply (bank 4) |
| Pino 82 | I/O — User I/O (bank 4) |
| Pino 83 | I/O — User I/O (bank 4) |
| Pino 84 | I/O — User I/O (bank 4) |
Aplicações típicas
EPM9320ALC84-15 é adequado para 6 aplicaçãos: 5 V Industrial PLC Glue Logic, ISA/PCI Bus Address Decoding & Chip-Select Generation, Motor Control State Machines, Telecom Backplane Control Logic, Legacy ASIC Replacement, Embedded System Glue Logic.
5 V Industrial PLC Glue Logic
The EPM9320ALC84-15 is well-suited to 5 V industrial PLC glue-logic integration: its 320 macrocells and 56 I/O easily absorb address decoding, peripheral chip-select generation, and timer/counter fan-out for legacy PLC backplanes. With a 16 ns worst-case tPD, the part deterministically meets timing of 25 MHz state machines commonly used in PLC scan loops. The 84-pin PLCC socket-mount format supports field-replacement and long-lifecycle industrial maintenance, while JTAG ISP allows firmware updates without removing the board. Compared with stitching multiple 22V10 SPLDs, this CPLD reduces board area and improves noise margin by replacing discrete glue logic with a single 5 V device.
Recomendado
ISA/PCI Bus Address Decoding & Chip-Select Generation
In ISA or PCI bus address decoding, the EPM9320ALC84-15's 56 I/O and 16 LABs provide enough macrocells to decode the full 24-bit address bus and generate 8 to 12 peripheral chip-selects in a single device. Its 16 ns tPD adds minimal latency to bus cycles, and the deterministic interconnect guarantees that any chip-select arrives within the same window regardless of which macrocell synthesizes it. Designers typically pair this part with 5 V-tolerant bus transceivers and use the JTAG port for ISP of updated decode maps. The PLCC-84 socket also makes this a common insertion point for legacy PC/104 and VMEbus controllers where the bus architecture predates modern PLD/FPGA tooling.
Recomendado
Motor Control State Machines
For stepper and BLDC motor control, the EPM9320ALC84-15 synthesizes the commutation state machine, PWM blanking logic, and fault handlers in a single 5 V device. With 16 LABs and 320 macrocells, the design can encode full sinusoidal commutation tables and quadrature decoders without external logic; the 16 ns tPD keeps the loop tight enough for 50 kHz PWM rates. The PLCC-84 package is preferred in motor drives for its thermal headroom at high ambient temperatures. JTAG ISP enables field updates of control firmware, while the deterministic timing ensures uniform PWM edge placement across all channels - critical for low-noise motor operation.
Recomendado
Telecom Backplane Control Logic
The EPM9320ALC84-15 integrates backplane control logic in T1/E1 and legacy SDH/SONET systems where 5 V tolerance and deterministic timing are required. Its 56 I/O can absorb clock-distribution trees, alarm-input scanning, and LED-status drivers that would otherwise require multiple PALs. The 16 ns tPD is comfortably fast for backplane housekeeping buses operating below 30 MHz, while the PLCC-84 package withstands the conformal coating and extended temperature of telecom cabinets. JTAG boundary-scan enables in-service board test, an important feature for the long service life of central-office equipment.
Recomendado
Legacy ASIC Replacement
The EPM9320ALC84-15 is a classic ASIC replacement for end-of-life gate arrays in long-lifecycle medical, aerospace, and industrial-control products. With 320 macrocells and 6 K usable gates, it absorbs medium-complexity ASICs from the 1990s, and the JTAG ISP interface allows last-minute design changes without re-spinning masks. The 84-PLCC socket simplifies field service and qualification - legacy ASICs in non-standard packages are notoriously hard to second-source. Designers keep the 16 ns tPD margin for legacy timing budgets while benefiting from a programmable, software-defined implementation that reduces NRE.
Recomendado
Embedded System Glue Logic
In embedded designs built around legacy x86, 68k, or PowerPC processors, the EPM9320ALC84-15 consolidates chip-select, wait-state, and interrupt-priority logic in a single 5 V device. The 56 user I/O handle eight to twelve peripheral selects plus interrupt controllers, and the 16 LABs accommodate address-decoding tables up to 16-bit wide. The deterministic 16 ns tPD ensures that processor-side accesses to slow peripherals remain within the bus-cycle budget. The PLCC-84 package is widely supported on embedded SBCs (PC/104, VME), and JTAG ISP allows remote firmware updates via boundary-scan tools in production.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM9320ALC84-15 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM9320ALC84-10 | EPM9320ALC84-10N | EPM9320LC84-15 | EPM9320LI84-15 |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 84-pin PLCC (S-PQCC-J84) | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Macrocells | 320 | 320 | 320 | 320 | 320 |
| Propagation Delay (tPD) | 16 ns | 10 ns | 10 ns | 16 ns | 16 ns |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Industrial (-40C to +85C) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| User I/O | 56 | 56 | 56 | 56 | 56 |
Principais diferenciais
- 320 macrocells in a single 84-PLCC package with deterministic 16 ns tPD (vs EPM9320ALC84-10)
- Industrial temperature grade (-40C to +85C) with EEPROM non-volatility (vs EPM9320LC84-15)
- In-system programmability via IEEE 1149.1 JTAG, no boot PROM required (vs EPM7160SLC84-10 (MAX 7000 family))
- 6 K usable gates with 16 LABs - higher density than 22V10/32V16 SPLDs (vs Multiple PALCE22V10 SPLDs)
Notas de projeto
The EPM9320ALC84-15 requires a single 4.75 V to 5.25 V supply with adequate decoupling. Place 0.1 uF ceramic bypass capacitors within 5 mm of each VCC pin (the 84-PLCC exposes VCC on pins 7, 15, 33, 53, 81). A bulk 10 uF tantalum or ceramic cap on the supply rail handles transient switching current during simultaneous I/O toggling. Estimated: at 56 I/O switching at 10 MHz, peak supply current can reach ~150 mA; budget for 300 mA worst case in the regulator. Connect all five GND pins (21, 41, 57, 68) directly to a low-impedance ground plane.
When laying out the 84-pin PLCC socket, fan out the inner ring of pins on the top layer with vias to an inner power/ground split plane. The MAX 9000's deterministic interconnect requires no special signal-integrity routing, but keep JTAG traces (TDI/TDO/TMS/TCK) short and isolated from switching outputs. Estimated: a 4-layer PCB with 1 oz copper and a 0.5 oz inner ground plane comfortably meets the 16 ns timing budget; for 10 ns drop-in operation use 2 oz copper on signal layers. Avoid 90-degree bends on clock pins GCLK1/GCLK2 to preserve duty cycle.
Do not confuse speed grade '15' (16 ns) with '10' (10 ns) or '12' (12 ns) - all three grades share the same 84-PLCC pinout and JTAG, but the tPD differs by up to 60%. For designs migrating from the MAX 7000 family, note that the MAX 9000 uses different programming files; re-compile in MAX+PLUS II or Quartus before loading the JTAG image. Estimated: typical I_OL/I_OH drive is 8 mA per pin in 5 V mode, sufficient for LED drive but inadequate for bus termination - place external buffers for backplane signals. Also note that the 'LC' suffix denotes commercial temperature, not 'lead-free'.
Informações de conformidade
ROHS3 Compliant per fpgalink.com listing (third-party distributor attestation). REACH and AEC-Q100 status not in verified data. Industrial temp grade (-40C to +85C) is appropriate for industrial but NOT automotive AEC-Q100 qualified.
