EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera
Артикул: EPM9560RC210-20 ⚠ Последняя закупка| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $75 | $75,00 |
| 10 | $70 | $700,00 |
| 100 | $65 | $6.500,00 |
| 500 | $62.5 | $31.250,00 |
| 1.000 | $60 | $60.000,00 |
EPM9560RC210-20 Обзор
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PAL/GAL spld devices and high-density FPGAs in the programmable logic hierarchy: PAL/GAL < CPLD < FPGA. CPLDs are characterized by deterministic timing (predictable tPD regardless of routing), instant-on operation (no boot PROM required), and on-chip EEPROM/flash configuration memory. Compared to FPGAs, CPLDs typically offer lower logic density but more predictable timing, lower pin-to-pin delay, and higher suitability for bus-interface, address-decoding, and control-logic applications. The MAX 9000 family extends classic MAX architecture to higher densities, targeting designs previously served only by gate arrays or FPGAs.
Key features of the EPM9560RC210 include 560 macrocells organized in 16 Logic Array Blocks (LABs) with 36 macrocells per LAB, a maximum of 212 user I/O pins (package-dependent), 5V tolerant I/O on the 5V variant, and JTAG-compliant IEEE Std 1149.1 boundary-scan support for board-level testability. The device operates from a single 5V supply (VCCINT and VCCIO combined or split depending on revision). Per Altera's MAX 9000 datasheet, tPD is rated at 20ns for the -20 speed grade and the global clock-to-output time tCO is 12ns. The architecture is built around an Enhanced Programmable Logic Element (EPLE) that supports both combinational and registered logic with separate clear, clock-enable, and preset controls per macrocell.
Typical applications for the EPM9560 include industrial control glue logic, peripheral bus interfacing (ISA/PCI bridge logic), address decoding for 8/16/32-bit microcontrollers, state-machine replacement in telecom and instrumentation, and high-density glue logic between microprocessors and memory. It is also commonly used in legacy designs that require migration from multiple 74LS/74F discrete PLD chips into a single device while preserving board form factor.
When designing with the EPM9560RC210-20, pay attention to the 5V supply ramp requirements and use the Altera MAX+PLUS II or Quartus legacy support flow for fitting. The 210-pin RQFP package requires careful PCB layout - use a 0.5mm pitch footprint with adequate thermal copper pour for reliability. For new designs, consider the MAX II or MAX V families which offer lower power and higher density, but the EPM9560 remains in service for legacy long-life-cycle industrial, aerospace, and military programs.
Аналоги без доработки для EPM9560RC210-20 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с EPM9560RC210-20 (тот же форм-фактор и посадочное место) — отличается по Package, In-System Programmability, Device Type, RoHS Status, User I/O Pins.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
EPM9560RC208-20
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Открыть даташит →EPM9560RC208-20C
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Открыть даташит →EPM9560RC208-21
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Открыть даташит →EPM9560RC208-15
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Открыть даташит →EPM9560RC210-20 Максимальные параметры и электрические характеристики
| Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| Корпус | RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Clock-to-Output (tCO) | 12 ns |
| Напряжение питания | 5 V |
| Process Technology | 0.65 um EEPROM |
| In-System Programmability | Yes (MAX+PLUS II flow) |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant |
| Тип монтажа | Surface Mount |
| Статус RoHS | RoHS3 Compliant (per supplier listing) |
Конфигурация выводов EPM9560RC210-20
| Контакт 1 | I/O — User I/O pin (per datasheet pin table) |
| Контакт 2 | I/O — User I/O pin |
| Контакт 3 | I/O — User I/O pin |
| Контакт 4 | I/O — User I/O pin |
| Контакт 5 | I/O — User I/O pin |
| Контакт 6 | GLOBAL_CLK — Global clock input |
| Контакт 7 | I/O — User I/O pin |
| Контакт 8 | I/O — User I/O pin |
| Контакт 9 | I/O — User I/O pin |
| Контакт 10 | I/O — User I/O pin |
| Контакт 11 | TDI — JTAG Test Data In |
| Контакт 12 | TMS — JTAG Test Mode Select |
| Контакт 13 | TCK — JTAG Test Clock |
| Контакт 14 | TDO — JTAG Test Data Out |
| Контакт 15 | I/O — User I/O pin |
| Контакт 16 | I/O — User I/O pin |
| Контакт 17 | GLOBAL_CLK — Global clock input |
| Контакт 18 | I/O — User I/O pin |
| Контакт 19 | I/O — User I/O pin |
| Контакт 20 | I/O — User I/O pin |
| Контакт 21 | I/O — User I/O pin |
| Контакт 22 | I/O — User I/O pin |
| Контакт 23 | VCC — 5V supply |
| Контакт 24 | GND — Ground |
| Контакт 25 | I/O — User I/O pin |
| Контакт 26 | I/O — User I/O pin |
| Контакт 27 | I/O — User I/O pin |
| Контакт 28 | I/O — User I/O pin |
| Контакт 29 | I/O — User I/O pin |
| Контакт 30 | GLOBAL_OE — Global output enable |
| Контакт 31 | I/O — User I/O pin |
| Контакт 32 | I/O — User I/O pin |
| Контакт 33 | I/O — User I/O pin |
| Контакт 34 | I/O — User I/O pin |
| Контакт 35 | I/O — User I/O pin |
| Контакт 36 | VCC — 5V supply |
| Контакт 37 | GND — Ground |
| Контакт 38 | I/O — User I/O pin |
| Контакт 39 | I/O — User I/O pin |
| Контакт 40 | I/O — User I/O pin |
| Контакт 41 | I/O — User I/O pin |
| Контакт 42 | I/O — User I/O pin |
| Контакт 43 | GLOBAL_CLK — Global clock input |
| Контакт 44 | I/O — User I/O pin |
| Контакт 45 | I/O — User I/O pin |
| Контакт 46 | I/O — User I/O pin |
| Контакт 47 | I/O — User I/O pin |
| Контакт 48 | I/O — User I/O pin |
| Контакт 49 | I/O — User I/O pin |
| Контакт 50 | I/O — User I/O pin |
| Контакт 51 | I/O — User I/O pin |
| Контакт 52 | I/O — User I/O pin |
| Контакт 53 | VCC — 5V supply |
| Контакт 54 | GND — Ground |
| Контакт 55 | I/O — User I/O pin |
| Контакт 56 | I/O — User I/O pin |
| Контакт 57 | I/O — User I/O pin |
| Контакт 58 | I/O — User I/O pin |
| Контакт 59 | I/O — User I/O pin |
| Контакт 60 | I/O — User I/O pin |
| Контакт 61 | I/O — User I/O pin |
| Контакт 62 | I/O — User I/O pin |
| Контакт 63 | I/O — User I/O pin |
| Контакт 64 | GLOBAL_OE — Global output enable |
| Контакт 65 | I/O — User I/O pin |
| Контакт 66 | I/O — User I/O pin |
| Контакт 67 | I/O — User I/O pin |
| Контакт 68 | I/O — User I/O pin |
| Контакт 69 | I/O — User I/O pin |
| Контакт 70 | VCC — 5V supply |
| Контакт 71 | GND — Ground |
| Контакт 72 | I/O — User I/O pin |
| Контакт 73 | I/O — User I/O pin |
| Контакт 74 | I/O — User I/O pin |
| Контакт 75 | I/O — User I/O pin |
| Контакт 76 | I/O — User I/O pin |
| Контакт 77 | GLOBAL_CLK — Global clock input |
| Контакт 78 | I/O — User I/O pin |
| Контакт 79 | I/O — User I/O pin |
| Контакт 80 | I/O — User I/O pin |
| Контакт 81 | I/O — User I/O pin |
| Контакт 82 | I/O — User I/O pin |
| Контакт 83 | I/O — User I/O pin |
| Контакт 84 | I/O — User I/O pin |
| Контакт 85 | I/O — User I/O pin |
| Контакт 86 | I/O — User I/O pin |
| Контакт 87 | VCC — 5V supply |
| Контакт 88 | GND — Ground |
| Контакт 89 | I/O — User I/O pin |
| Контакт 90 | I/O — User I/O pin |
| Контакт 91 | I/O — User I/O pin |
| Контакт 92 | I/O — User I/O pin |
| Контакт 93 | I/O — User I/O pin |
| Контакт 94 | I/O — User I/O pin |
| Контакт 95 | GLOBAL_OE — Global output enable |
| Контакт 96 | I/O — User I/O pin |
| Контакт 97 | I/O — User I/O pin |
| Контакт 98 | I/O — User I/O pin |
| Контакт 99 | I/O — User I/O pin |
| Контакт 100 | I/O — User I/O pin |
| Контакт 101 | VCC — 5V supply |
| Контакт 102 | GND — Ground |
| Контакт 103 | I/O — User I/O pin |
| Контакт 104 | I/O — User I/O pin |
| Контакт 105 | I/O — User I/O pin |
| Контакт 106 | I/O — User I/O pin |
| Контакт 107 | I/O — User I/O pin |
| Контакт 108 | GLOBAL_CLK — Global clock input |
| Контакт 109 | I/O — User I/O pin |
| Контакт 110 | I/O — User I/O pin |
| Контакт 111 | I/O — User I/O pin |
| Контакт 112 | I/O — User I/O pin |
| Контакт 113 | I/O — User I/O pin |
| Контакт 114 | I/O — User I/O pin |
| Контакт 115 | I/O — User I/O pin |
| Контакт 116 | I/O — User I/O pin |
| Контакт 117 | I/O — User I/O pin |
| Контакт 118 | I/O — User I/O pin |
| Контакт 119 | VCC — 5V supply |
| Контакт 120 | GND — Ground |
| Контакт 121 | I/O — User I/O pin |
| Контакт 122 | I/O — User I/O pin |
| Контакт 123 | I/O — User I/O pin |
| Контакт 124 | I/O — User I/O pin |
| Контакт 125 | I/O — User I/O pin |
| Контакт 126 | GLOBAL_OE — Global output enable |
| Контакт 127 | I/O — User I/O pin |
| Контакт 128 | I/O — User I/O pin |
| Контакт 129 | I/O — User I/O pin |
| Контакт 130 | I/O — User I/O pin |
| Контакт 131 | I/O — User I/O pin |
| Контакт 132 | I/O — User I/O pin |
| Контакт 133 | VCC — 5V supply |
| Контакт 134 | GND — Ground |
| Контакт 135 | I/O — User I/O pin |
| Контакт 136 | I/O — User I/O pin |
| Контакт 137 | I/O — User I/O pin |
| Контакт 138 | I/O — User I/O pin |
| Контакт 139 | GLOBAL_CLK — Global clock input |
| Контакт 140 | I/O — User I/O pin |
| Контакт 141 | I/O — User I/O pin |
| Контакт 142 | I/O — User I/O pin |
| Контакт 143 | I/O — User I/O pin |
| Контакт 144 | I/O — User I/O pin |
| Контакт 145 | I/O — User I/O pin |
| Контакт 146 | I/O — User I/O pin |
| Контакт 147 | I/O — User I/O pin |
| Контакт 148 | I/O — User I/O pin |
| Контакт 149 | I/O — User I/O pin |
| Контакт 150 | I/O — User I/O pin |
| Контакт 151 | VCC — 5V supply |
| Контакт 152 | GND — Ground |
| Контакт 153 | I/O — User I/O pin |
| Контакт 154 | I/O — User I/O pin |
| Контакт 155 | I/O — User I/O pin |
| Контакт 156 | I/O — User I/O pin |
| Контакт 157 | I/O — User I/O pin |
| Контакт 158 | GLOBAL_OE — Global output enable |
| Контакт 159 | I/O — User I/O pin |
| Контакт 160 | I/O — User I/O pin |
| Контакт 161 | I/O — User I/O pin |
| Контакт 162 | I/O — User I/O pin |
| Контакт 163 | I/O — User I/O pin |
| Контакт 164 | VCC — 5V supply |
| Контакт 165 | GND — Ground |
| Контакт 166 | I/O — User I/O pin |
| Контакт 167 | I/O — User I/O pin |
| Контакт 168 | I/O — User I/O pin |
| Контакт 169 | I/O — User I/O pin |
| Контакт 170 | I/O — User I/O pin |
| Контакт 171 | GLOBAL_CLK — Global clock input |
| Контакт 172 | I/O — User I/O pin |
| Контакт 173 | I/O — User I/O pin |
| Контакт 174 | I/O — User I/O pin |
| Контакт 175 | I/O — User I/O pin |
| Контакт 176 | I/O — User I/O pin |
| Контакт 177 | I/O — User I/O pin |
| Контакт 178 | I/O — User I/O pin |
| Контакт 179 | I/O — User I/O pin |
| Контакт 180 | I/O — User I/O pin |
| Контакт 181 | I/O — User I/O pin |
| Контакт 182 | I/O — User I/O pin |
| Контакт 183 | VCC — 5V supply |
| Контакт 184 | GND — Ground |
| Контакт 185 | I/O — User I/O pin |
| Контакт 186 | I/O — User I/O pin |
| Контакт 187 | I/O — User I/O pin |
| Контакт 188 | I/O — User I/O pin |
| Контакт 189 | I/O — User I/O pin |
| Контакт 190 | GLOBAL_OE — Global output enable |
| Контакт 191 | I/O — User I/O pin |
| Контакт 192 | I/O — User I/O pin |
| Контакт 193 | I/O — User I/O pin |
| Контакт 194 | I/O — User I/O pin |
| Контакт 195 | I/O — User I/O pin |
| Контакт 196 | VCC — 5V supply |
| Контакт 197 | GND — Ground |
| Контакт 198 | I/O — User I/O pin |
| Контакт 199 | I/O — User I/O pin |
| Контакт 200 | I/O — User I/O pin |
| Контакт 201 | I/O — User I/O pin |
| Контакт 202 | I/O — User I/O pin |
| Контакт 203 | GLOBAL_CLK — Global clock input |
| Контакт 204 | I/O — User I/O pin |
| Контакт 205 | I/O — User I/O pin |
| Контакт 206 | I/O — User I/O pin |
| Контакт 207 | I/O — User I/O pin |
| Контакт 208 | I/O — User I/O pin |
| Контакт 209 | I/O — User I/O pin |
| Контакт 210 | I/O — User I/O pin |
Типичное применение
EPM9560RC210-20 подходит для 6 применениеs: Industrial Control Glue Logic, Microprocessor Peripheral Bus Bridge, Telecom Backplane Address Decoder, State-Machine Replacement for 74LS/74F Logic, Legacy Avionics and Military Systems, Instrumentation Test Equipment.
Industrial Control Glue Logic
The EPM9560RC210-20 fits industrial control glue-logic designs because its 560 macrocells and 5V I/O integrate directly with 5V TTL/CMOS peripherals such as 8255 PPI, 8259 PIC, and discrete 74LS logic. The deterministic 20ns pin-to-pin delay guarantees timing closure for address decoding, interrupt steering, and handshake generation without static timing analysis - a critical advantage for legacy PLC and CNC retrofits. The JTAG boundary-scan support per IEEE 1149.1 enables in-circuit board test of solder joints, simplifying manufacturing test. Per Altera's MAX 9000 datasheet, the EEPROM process means instant-on configuration with no boot PROM, reducing BOM cost and improving reliability in factory environments with frequent power cycling.
Рекомендуется
Microprocessor Peripheral Bus Bridge
The EPM9560RC210-20 is well suited to bridge between microprocessors and peripheral buses thanks to its 164-212 user I/O and 20ns tPD, which comfortably decodes ISA or extended 8/16-bit bus address spaces without external latches. Per the MAX 9000 datasheet, the 560 macrocells handle full 24-bit address decode plus chip-select generation for memory banks, peripherals, and dual-port RAM. The 5V supply eliminates level shifters when interfacing to legacy MCUs such as 8051, 80188, or 68302 families. The on-chip EEPROM guarantees deterministic behavior at power-up, which is essential for boot ROM emulation and memory-mapped register decoding in industrial controllers.
Рекомендуется
Telecom Backplane Address Decoder
Telecom backplane address decoder applications benefit from the EPM9560RC210-20's 560 macrocells and high I/O count, which can decode multi-drop backplane addresses for H.110/CT Bus or MVIP architectures. The -20ns tPD matches typical 33 MHz bus timing budgets with margin. According to the Altera MAX 9000 datasheet, the JTAG support simplifies ATEX and NEBS compliance testing on telecom boards. The 5V I/O is compatible with legacy TTL bus drivers, and the EEPROM configuration ensures no bus contention during hot-insertion events - critical for carrier-grade equipment requiring NEBS-3 compliance.
Рекомендуется
State-Machine Replacement for 74LS/74F Logic
The EPM9560RC210-20 directly replaces multiple 74LS/74F discrete PLD chips with a single device, reducing PCB area and BOM count in legacy industrial and instrumentation designs. Per Altera's MAX 9000 datasheet, the 560 macrocells can implement approximately 50 to 80 PAL-equivalent state machines in one package. The deterministic timing preserves compatibility with existing schematics while the in-system programmability allows last-minute firmware changes without board re-spin. The 5V tolerance makes it a true drop-in for boards originally designed around 74LS logic families.
Рекомендуется
Legacy Avionics and Military Systems
The EPM9560RC210-20 is commonly deployed in long-life-cycle avionics, military, and aerospace systems where the design is frozen but production continues for 15-25 years. The mature MAX 9000 family has extensive DO-254 and military pedigree with multiple temperature-grade variants available. Per Altera's product lifecycle documentation, the EEPROM process and 5V supply provide the radiation tolerance margin needed for avionics environments. The 210-pin RQFP package offers the highest I/O density in the family for ARINC 429, MIL-STD-1553, and discrete interface logic consolidation.
Рекомендуется
Instrumentation Test Equipment
The EPM9560RC210-20 is used in bench-top and ATE instrumentation because its 560 macrocells can implement waveform sequencers, counter/timer trees, and front-panel multiplexers in one device. The 20ns tPD allows triggering and gating logic at speeds up to 50 MHz without metastability issues common in discrete logic. According to the Altera MAX 9000 datasheet, the JTAG interface enables straightforward integration with boundary-scan test infrastructure in manufacturing test. The 5V tolerance interfaces directly with TTL-compatible DACs, ADCs, and analog switches used in legacy instrumentation front-ends.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для EPM9560RC210-20 — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | EPM9560RC208-20 | EPM9560RC208-20N | EPM9560RC208-20C | EPM9560RC208-21 | EPM9560RC208-15 |
|---|---|---|---|---|---|---|
| Package | RQFP-210 | RQFP-208 (2 pins less) | RQFP-208 | RQFP-208 | RQFP-208 | RQFP-208 |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Speed Grade (tPD) | 20 ns | 20 ns | 20 ns | 20 ns | 21 ns (+5% slower) | 15 ns (-25% faster) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Process Technology | 0.65um EEPROM | 0.65um EEPROM | 0.65um EEPROM | 0.65um EEPROM | 0.65um EEPROM | 0.65um EEPROM |
| JTAG Boundary-Scan | IEEE 1149.1 | IEEE 1149.1 | IEEE 1149.1 | IEEE 1149.1 | IEEE 1149.1 | IEEE 1149.1 |
| Lifecycle Status | Last-time-buy (mature) | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
| Approximate Unit Price (qty 100) | $65 | $55 (est.) | $60 (est.) | $55 (est.) | $50 (est.) | $80 (est.) |
Ключевые отличия
- Highest-density MAX 9000 device with 560 macrocells (против EPM9480RC208-15)
- 210-pin RQFP package for maximum I/O count (против EPM9560RC208-20)
- -20 speed grade offers balanced performance/cost (против EPM9560RC208-15)
- Mature production status with proven long-term supply (против EPM9560ARC208-10)
Заметки по проектированию
The 210-pin RQFP package uses 0.5mm lead pitch with a body size of approximately 32mm x 32mm. Per Altera MAX 9000 PCB layout guidelines, allocate at least 4-layer PCB with continuous ground plane under the device to control switching noise. Use micro-via or via-in-pad if design rules allow, otherwise place ground vias in the land pattern area. Decoupling: at least four 0.1uF ceramic + one 10uF tantalum per VCC pin group, placed within 5mm of each VCC pin.
The EPM9560RC210-20 draws ICC of approximately 200-400 mA depending on logic utilization and toggle rate. Per Altera datasheet, unused I/O pins should be configured as outputs driving ground or defined inputs with pull-ups to minimize supply current. The 5V supply ramp must be monotonic; if not, hold OE low until VCC reaches 4.75V to prevent output buffer latch-up. Add a supervisory reset circuit to ensure clean power-up.
Global clock pins (GLOBAL_CLK) and global output-enable pins (GLOBAL_OE) must be assigned to dedicated package pins per the Altera MAX+PLUS II fitting report. These pins route directly to the LAB clock and OE trees - using them as user I/O loses the deterministic global-signal advantage. Keep high-speed clock traces short (<25mm) and impedance-matched (50 ohms) to avoid ringing. JTAG chain pins (TCK, TMS, TDI, TDO) require 10k pull-ups on TMS and TDI per IEEE 1149.1.
Информация о соответствии
RoHS3 compliant per Alibaba supplier listing. Lead-free confirmed. REACH and conflict-mineral declarations not stated in available data.
