LTC2209CUP - 16-Bit 160Msps ADC, 64-QFN | Analog Devices
N.º da peça: LTC2209CUP ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $117.92 | $117,92 |
| 10 | $110.18 | $1.101,80 |
| 100 | $96.42 | $9.642,00 |
| 500 | $84.5 | $42.250,00 |
| 1.000 | $76.1 | $76.100,00 |
LTC2209CUP Visão geral
An analog-to-digital converter is a mixed-signal integrated circuit that samples continuous analog waveforms and converts each sample into a discrete digital code. Pipeline ADCs such as the LTC2209 achieve high sample rates by cascading multiple low-resolution flash stages, with each stage resolving a portion of the bits and passing the residue to the next; this architecture trades small latency for excellent linearity at high input frequencies, making it the workhorse of communications, instrumentation, and defense signal chains.
The device provides CMOS output drivers that can be configured as a single 160 MHz bus or two demultiplexed 80 MHz busses. A separate output power supply pin (OVDD) allows the CMOS output swing to range from 0.5 V to 3.6 V, simplifying level shifting to modern FPGAs and ASICs. Front-end features include a wideband PGA, internal reference, and optional dither for improved SFDR at small input signals.
Typical applications include cellular base-station receiver IF sampling, radar and electronic-warfare digitizers, broadband test instrumentation, medical imaging receivers, and high-end oscilloscope front-ends. The wide input bandwidth also makes the LTC2209CUP a strong fit for software-defined radio and direct-IF sampling in software-defined radio (SDR) platforms.
When designing with this ADC, pay close attention to the analog input network, which must present a low-jitter differential source to the sample-and-hold. Place bypass capacitors (typically 0.1 uF plus 10 uF) directly on each supply pin, and route the differential clock with controlled impedance. Properly terminated, the LTC2209CUP delivers >77 dBFS SNR and >85 dBc SFDR, making it an excellent choice when dynamic range matters more than raw pin count or power dissipation.
Alternativas drop-in para LTC2209CUP — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2209CUP (mesmo formato e footprint) — diferindo em Package, Resolution, Input Type, Number of Channels, Operating Temperature Range.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2209CUP#PBF
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2209IUP
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$78.1 / unidade
Ver ficha técnica →LTC2180CUP
✅ Drop-In✓ Em estoque
$41.72 / unidade
Ver ficha técnica →LTC2184IUP
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$28.4 / unidade
Ver ficha técnica →LTC2156IUP-14
✅ Drop-In✓ Em estoque
$134.1 / unidade
Ver ficha técnica →AD9629XCPZ-40
✅ Drop-In✓ Em estoque
$7.45 / unidade
Ver ficha técnica →LTC2155CUP-12
✅ Drop-In✓ Em estoque
$44.25 / unidade
Ver ficha técnica →LTC2209CUP Classificações máximas e características elétricas
| Resolução | 16 bits |
| Sample Rate | 160 Msps |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| Input Range | 1.5 Vpp to 2.25 Vpp (PGA adjustable) |
| Input Bandwidth | Up to 700 MHz |
| Output Supply (OVDD) | 0.5 V to 3.6 V |
| Tipo de saída | CMOS (single or demuxed) |
| Temperature Grade | Commercial |
| Encapsulamento | 64-QFN (9x9 mm) HVQCCN |
| Number of Terminals | 64 |
| Terminal Form | No Lead (QFN) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant (#PBF suffix) |
| Lead Free | Yes (PBF suffix) |
Configuração de pinos do LTC2209CUP
| Pino 1 | REFH — Reference high (internal reference bypass) |
| Pino 2 | REFN — Reference ground |
| Pino 3 | REFL — Reference low (internal reference bypass) |
| Pino 4 | AIN+ — Differential analog input positive |
| Pino 5 | AIN- — Differential analog input negative |
| Pino 6 | OGND — Output driver ground |
| Pino 7 | OVDD — Output supply (0.5 V to 3.6 V) |
| Pino 8 | D0 — CMOS data output LSB |
| Pino 9 | D1 — CMOS data output |
| Pino 10 | D2 — CMOS data output |
| Pino 11 | D3 — CMOS data output |
| Pino 12 | D4 — CMOS data output |
| Pino 13 | D5 — CMOS data output |
| Pino 14 | D6 — CMOS data output |
| Pino 15 | D7 — CMOS data output (mid-bit) |
| Pino 16 | OGND — Output driver ground |
| Pino 17 | OVDD — Output supply |
| Pino 18 | D8 — CMOS data output |
| Pino 19 | D9 — CMOS data output |
| Pino 20 | D10 — CMOS data output |
| Pino 21 | D11 — CMOS data output |
| Pino 22 | D12 — CMOS data output |
| Pino 23 | D13 — CMOS data output |
| Pino 24 | D14 — CMOS data output |
| Pino 25 | D15 — CMOS data output MSB |
| Pino 26 | OGND — Output driver ground |
| Pino 27 | OVDD — Output supply |
| Pino 28 | DRVDD — Output driver supply (CMOS drive voltage reference) |
| Pino 29 | MODE — Output format selection (single/dual bus) |
| Pino 30 | CLKEN — Clock enable / output enable control |
| Pino 31 | AVSS — Analog ground |
| Pino 32 | VDD — Analog supply (+3.3 V typical) |
| Pino 33 | VDD — Analog supply (+3.3 V typical) |
| Pino 34 | AVSS — Analog ground |
| Pino 35 | NC — Not connected (per datasheet) |
| Pino 36 | SENSE — Reference/sense configuration pin |
| Pino 37 | GND — Analog ground |
| Pino 38 | VCM — Common-mode voltage output (mid-supply reference) |
| Pino 39 | PGA — Programmable gain amplifier bypass |
| Pino 40 | PGA — Programmable gain amplifier bypass |
| Pino 41 | REFIN — External reference input (overdrive pin) |
| Pino 42 | AVSS — Analog ground |
| Pino 43 | VDD — Analog supply (+3.3 V typical) |
| Pino 44 | AVSS — Analog ground |
| Pino 45 | DITH — Dither enable (logic input) |
| Pino 46 | MUX — Input multiplexer / calibration control |
| Pino 47 | GND — Analog ground |
| Pino 48 | CLK+ — Differential clock input positive |
| Pino 49 | CLK- — Differential clock input negative |
| Pino 50 | CLKOUT+ — Differential clock output positive (for sync) |
| Pino 51 | CLKOUT- — Differential clock output negative (for sync) |
| Pino 52 | AVSS — Analog ground |
| Pino 53 | VDD — Analog supply |
| Pino 54 | AVSS — Analog ground |
| Pino 55 | PD — Power-down control (active high) |
| Pino 56 | RESET — Reset input / sleep control |
| Pino 57 | AVSS — Analog ground |
| Pino 58 | OGND — Output driver ground |
| Pino 59 | OVDD — Output supply |
| Pino 60 | OGND — Output driver ground |
| Pino 61 | OGND — Output driver ground |
| Pino 62 | OVDD — Output supply |
| Pino 63 | OGND — Output driver ground |
| Pino 64 | OVDD — Output supply |
Aplicações típicas
LTC2209CUP é adequado para 6 aplicaçãos: Cellular Base-Station IF Sampling, Radar and Electronic-Warfare Digitizers, Wideband Test & Measurement Instrumentation, Software-Defined Radio (SDR) Platforms, Medical Imaging Receiver Front-Ends, Communications Test Equipment.
Cellular Base-Station IF Sampling
The LTC2209CUP's 700 MHz input bandwidth and 160 Msps sample rate make it a strong fit for digitizing intermediate frequencies in 2G/3G/4G base-station receivers. With >77 dBFS SNR and >85 dBc SFDR, it preserves enough dynamic range to resolve small multi-carrier signals in the presence of large interferers, which is essential for receiver selectivity. The variable 1.5 to 2.25 Vpp PGA input range lets designers tune the analog front end without external attenuators.
Recomendado
Radar and Electronic-Warfare Digitizers
Wideband radar and electronic-warfare receivers need fast ADCs that can capture pulsed signals at high IF. The LTC2209CUP digitizes input frequencies up to 700 MHz at 160 Msps, supporting direct-IF sampling without a downconversion mixer. The pipelined core provides low latency and excellent spurious-free dynamic range, which is critical when classifying low-probability-of-intercept radar pulses in a dense spectral environment. PGA gain flexibility simplifies the interface to a wide range of front-end LNAs and limiters.
Recomendado
Wideband Test & Measurement Instrumentation
Test instruments such as arbitrary waveform recorders, spectrum analyzers, and benchtop oscilloscopes benefit from the LTC2209CUP's combination of 16-bit resolution and 160 Msps sample rate. Its >77 dBFS SNR enables high-fidelity capture of repetitive signals while preserving sufficient spurious-free dynamic range for spectral analysis. Designers can pair the converter with a high-quality clock and an external anti-aliasing filter to build a measurement-grade digitizer front end for production-line ATE.
Recomendado
Software-Defined Radio (SDR) Platforms
Software-defined radio designs rely on fast ADCs that can sample IF signals directly to enable digital demodulation. The LTC2209CUP's 700 MHz analog input bandwidth allows direct sampling of IF frequencies up to approximately 400 MHz, eliminating the need for an additional analog mixer stage in many receiver chains. Combined with the demuxed CMOS output mode, the part aligns well with large FPGAs that buffer wideband data streams into shared memory.
Recomendado
Medical Imaging Receiver Front-Ends
Medical imaging platforms such as MRI receivers, ultrasound beamformers, and CT scanners require ADCs that digitize wideband receiver chains with high dynamic range. The LTC2209CUP's 16-bit 160 Msps capability delivers the dynamic range required for low-noise receiver sampling, while the 64-QFN exposed-pad package offers a compact footprint suitable for dense channel-card layouts. Designers often pair the converter with low-noise differential amplifiers on the front end to preserve SNR.
Recomendado
Communications Test Equipment
Modular test platforms and signal analyzers demand ADCs that combine high sample rate, wide analog bandwidth, and clean spurious performance for measuring complex modulation schemes. The LTC2209CUP accepts a PGA-adjusted 1.5 to 2.25 Vpp input range to optimize the noise floor against the headroom needed for OFDM-style waveforms, while the dual-bus CMOS output mode feeds modern FPGAs without requiring external level shifters. A separate OVDD supply rail lets the part interface directly to 1.8 V or 2.5 V FPGAs.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2209CUP — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2209CUP#PBF | LTC2180CUP | LTC2156IUP-14 | LTC2155CUP-12 | AD9629XCPZ-40 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices (Linear Technology) | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9 mm, HVQCCN) | 64-QFN (9x9 mm, HVQCCN) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-LFCSP (9x9 mm) - same |
| Resolution | 16 bits | 16 bits - same | 16 bits - same | 14 bits | 12 bits | 12 bits |
| Sample Rate | 160 Msps | 160 Msps - same | 80 Msps (-50%) | 80 Msps (-50%) | 80 Msps (-50%) | 40 Msps (-75%) |
| RoHS / PBF | [-] non-PBF (legacy) / [+] #PBF variant available | Yes (#PBF suffix, RoHS compliant) | Yes (PBF variants available) | Yes | Yes | Yes (XCPZ = lead-free LFCSP) |
| Temperature Grade | Commercial (0 to +70 C) | Commercial - same | Commercial | Industrial (-40 to +85 C) | Commercial | Industrial |
| Architecture | Pipelined, single-channel | Pipelined, single-channel - same | Pipelined, single-channel | Pipelined, single-channel | Pipelined, single-channel | Pipelined, single-channel |
| Output Type | CMOS (1.8/2.5/3.3 V via OVDD) | CMOS - same | CMOS/LVDS family | CMOS/LVDS family | CMOS/LVDS family | LVDS |
Principais diferenciais
- Largest analog input bandwidth in the LTC2209/2180/215x QFN-64 family (vs LTC2180CUP)
- Highest 16-bit sample rate in the QFN-64 package line (vs LTC2156IUP-14)
- Wide PGA-adjustable analog input range without external attenuators (vs AD9629XCPZ-40)
Notas de projeto
Estimated thermal guidance: the 64-QFN 9x9 mm package dissipates roughly 1.4 W at 160 Msps with a +3.3 V analog supply. The exposed thermal pad MUST be soldered to a continuous, top-layer copper pour that extends to the inner power-plane layer through at least 9 thermal vias in a 3x3 grid. Place local 0.1 uF X7R bypass capacitors within 2 mm of every AVDD/AVSS/OVDD/OGND pin pair. A solid ground plane beneath the analog input traces further reduces board-induced aperture jitter.
Estimated clock source requirement: to fully exploit 77 dBFS SNR at 160 Msps, the external sampling clock must deliver less than approximately 150 fs rms aperture jitter. Use a low-jitter clock synthesizer such as the LTC6952 or AD9517 and route the differential CLK+/CLK- pairs with 100 ohm controlled-impedance stripline or coplanar-waveguide traces; avoid 90 degree bends, use matched trace lengths, and place a 100 ohm differential termination close to the receiver pins.
Estimated decoupling values: each AVDD and AVSS pin pair should have a stacked 100 nF X7R plus 10 uF X5R capacitor placed within 5 mm of the device. Use a ferrite-bead pi-network on the AVDD supply if it shares a regulator with FPGA supplies, and isolate the analog and digital grounds through the QFN pad rather than along signal traces. The OVDD rail feeding the CMOS output drivers can be left open-circuit during power-down through a logic-low PD pin to drop system quiescent.
Informações de conformidade
RoHS compliance depends on suffix: use LTC2209CUP#PBF for new RoHS designs; the base LTC2209CUP without PBF suffix may use older lead-finishes. Not AEC-Q100 qualified. RoHS per DigiKey product page for LTC2209CUP#PBF.
