Intel

EPM9320ALC84-10N - 320-Macrocell MAX 9000 CPLD, 10ns, 84-PLCC

Артикул: EPM9320ALC84-10N ✗ Снят с производства
В наличии Отправка в течение 1–3 рабочих дней
5.0 V nominal Vdss 84-Pin PLCC (Plastic Leaded Chip Carrier) Package 144.9 MHz Speed
От $21.4 USD / шт.
MOQ: 1 |
Цена обновлена: 2026-09-12
Оптовые цены
Кол-во Цена за ед. Итого
1 $38.5 $38,50
10 $34.2 $342,00
100 $28.95 $2.895,00
500 $24.6 $12.300,00
1.000 $21.4 $21.400,00
ℹ️ Все цены указаны в USD

EPM9320ALC84-10N Обзор

The Intel (formerly Altera) EPM9320ALC84-10N is a 320-macrocell, 6,000-gate CMOS Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. The -10 speed grade corresponds to a 10 ns pin-to-pin delay, and the device supports an internal toggle frequency up to 144.9 MHz at 5 V operation. The MAX 9000A family combines high density, in-system programmability, and predictable interconnect timing for glue-logic, bus-interface, and state-machine consolidation designs.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits hierarchically between simple PAL/GAL splds and high-density FPGAs. It provides predictable timing, instant-on operation, and high fan-in macrocell structures, making it ideal for deterministic control logic. CPLDs are typically used for address decoding, peripheral interfacing, bus bridging, and power-sequencing controllers where fixed, low-latency response is required. The MAX 9000 family extends classic EPLD architecture to higher logic densities while retaining the deterministic timing that made the MAX 5000 and MAX 7000 families popular in telecom, industrial, and embedded designs.

Key features of the EPM9320ALC84-10N include 320 macrocells distributed across 16 logic array blocks (LABs), 60 user I/O pins, 5 V core operation (5.0 V nominal VCC), in-system programmability via JTAG (IEEE 1149.1), and a commercial 0C to 70C operating temperature range. The device includes per-macrocell registers, programmable interconnect array (PIA), and dedicated input/output control blocks. The 84-pin PLCC package provides through-hole compatibility for legacy industrial backplanes, retrofit designs, and existing production assemblies where socket replacement is preferable to redesign.

From an architectural standpoint, the EPM9320A uses Altera's classic MAX architecture with EEPROM-based configuration cells, meaning the device retains its programmed logic without external boot memory. Configuration is loaded via JTAG using a ByteBlaster or compatible programmer, and the part can be reprogrammed thousands of times. The 10 ns tPD and 144.9 MHz fCNT make this part suitable for state machines running at moderate clock rates and for pipelined control logic.

Typical applications include legacy industrial control boards, telecom line-card glue logic, address-decoding and chip-select generation, peripheral bus interfacing (ISA, PCI, VME), motor-control state machines, and retrofit/repair scenarios where the original MAX 9000 part must be replaced. The part is also widely used in educational boards, prototype development, and military/aerospace systems where the MAX 9000 family has long design-cycle approval.

When designing with the EPM9320ALC84-10N, observe the recommended 5.0 V VCC tolerance (the A-suffix denotes 5 V operation, not the 3.3 V-compatible LC/RC/QI variants). Decouple each VCC/ground pair with a 0.1 F ceramic capacitor placed within 50 mils of the package pin, and adhere to the JTAG chain layout guidelines for multi-device boundary-scan configurations. The 84-PLCC socket should be a low-profile machine-pin or open-frame type rated for the operating temperature range.

This page synthesizes distributor pricing, drop-in alternatives drawn from the same MAX 9000 family, and practical design notes not found in the manufacturer datasheet alone.

Аналоги без доработки для EPM9320ALC84-10N — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPM9320ALC84-10N (тот же форм-фактор и посадочное место) — отличается по Package, Mounting Type, Architecture, Process Technology, Supply Voltage (VCC).

Intel
Package: 84-pin PLCC (J-Lead)
Mounting Type: Surface Mount / Through-Hole (PLCC socket)
Architecture: MAX (Multiple Array MatriX) with FastTrack Interconnect
Сравнить с EPM9320ALC84-10N →
Altera
Package: 84-pin PLCC (S-PQCC-J84, J-lead)
Supply Voltage (VCC): 4.75 V to 5.25 V (5 V nominal)
Сравнить с EPM9320ALC84-10N →
Altera
Package: PLCC-84
Mounting Type: Surface Mount (PLCC socket compatible)
Process Technology: 0.5 µm CMOS EEPROM
Сравнить с EPM9320ALC84-10N →
Intel
Mounting Type: Surface Mount (PLCC socket compatible)
Architecture: Multiple Array MatriX (MAX)
Process Technology: CMOS
Сравнить с EPM9320ALC84-10N →
Altera
Package: 84-pin PLCC (J-lead, 1.270 mm pitch)
Mounting Type: Surface Mount (PLCC socket compatible)
Architecture: MAX (Multiple Array MatriX), 3rd generation
Сравнить с EPM9320ALC84-10N →
Intel
Package: 84-pin PLCC (JEDEC MO-047)
Mounting Type: Surface Mount (PLCC socket also common)
Process Technology: 0.7 µm CMOS EEPROM/UV-EPROM
Сравнить с EPM9320ALC84-10N →
Intel
Mounting Type: Surface Mount
Supply Voltage (VCC): 4.75 V to 5.25 V (5.0 V nominal)
Сравнить с EPM9320ALC84-10N →
Altera
Package: PLCC-84 (Plastic Leaded Chip Carrier)
Architecture: Multiple Array MatriX (MAX), 3rd generation
Сравнить с EPM9320ALC84-10N →
Altera
Package: 84-PLCC (J-Lead, plastic LCC)
Mounting Type: Surface Mount (PLCC socket-compatible)
Architecture: Multiple Array MatriX (MAX) - third generation
Сравнить с EPM9320ALC84-10N →

Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:

EPM9320ALC84-10

✅ Прямая замена
Intel
📦 84-PLCC
MAX 9000 · EPM9320 · 320 · 16 · 52 · 16 · -10 (10 ns pin-to-pin delay) · 10 ns

✓ В наличии

$19.8 / шт.

Открыть даташит →

EPM9320ALI84-10

✅ Прямая замена
Intel
📦 84-PLCC
MAX 9000 · CPLD (Complex Programmable Logic Device) · 6,000 to 12,000 · 320 · 84 · 84-pin PLCC (Plastic Leaded Chip Carrier) · 10 ns · 144 MHz

✓ В наличии

$19.95 / шт.

Открыть даташит →

EPM9320LC84-15

✅ Прямая замена
Intel
📦 84-PLCC
MAX 9000 · EPM9320 · CPLD (Complex Programmable Logic Device) · 320 · 6,000 · 20 · 15 ns (max) · 117.6 MHz

✓ В наличии

$17.95 / шт.

Открыть даташит →

EPM9320LC84-20

✅ Прямая замена
Altera
📦 84-PLCC
MAX 9000 · CPLD - Complex Programmable Logic Device · 320 · 60 · CMOS (EEPROM-based) · PLCC-84 (Plastic Leaded Chip Carrier) · 84 · 16 ns

✓ В наличии

$9.75 / шт.

Открыть даташит →

EPM9320LI84-20

✅ Прямая замена
Altera
📦 84-PLCC
Altera (acquired by Intel) · MAX 9000 · CPLD (Complex Programmable Logic Device) · 320 · 60 · 84-PLCC (J-Lead, plastic LCC) · 20 ns · 118 MHz

✓ В наличии

$12.8 / шт.

Открыть даташит →

EPM9320ALC84-10N Максимальные параметры и электрические характеристики

Series MAX 9000A
Family MAX 9000
Device Type CPLD (Complex Programmable Logic Device)
Number of Macrocells 320
Number of Gates 6,000
Number of Logic Array Blocks (LABs) 16
User I/O Pins 60
Propagation Delay (tPD) 10 ns
Maximum Internal Frequency (fCNT) 144.9 MHz
Supply Voltage (VCC) 5.0 V nominal
Диапазон рабочих температур 0C to +70C (Commercial)
Programmable Technology EEPROM (in-system programmable)
Programming Interface JTAG (IEEE 1149.1)
Корпус 84-Pin PLCC (Plastic Leaded Chip Carrier)
Тип монтажа Through-Hole / Socket
Part Status Obsolete

Конфигурация выводов EPM9320ALC84-10N

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Контакт 1 I/O — User I/O pin (function depends on user design)
Контакт 2 I/O — User I/O pin
Контакт 3 I/O — User I/O pin
Контакт 4 I/O — User I/O pin
Контакт 5 I/O — User I/O pin
Контакт 6 I/O — User I/O pin
Контакт 7 VCC — 5.0 V supply voltage
Контакт 8 I/O — User I/O pin
Контакт 9 I/O — User I/O pin
Контакт 10 I/O — User I/O pin
Контакт 11 GND — Ground reference
Контакт 12 I/O — User I/O pin
Контакт 13 I/O — User I/O pin
Контакт 14 I/O — User I/O pin
Контакт 15 TMS — JTAG Test Mode Select
Контакт 16 TCK — JTAG Test Clock
Контакт 17 I/O — User I/O pin
Контакт 18 I/O — User I/O pin
Контакт 19 I/O — User I/O pin
Контакт 20 I/O — User I/O pin
Контакт 21 I/O — User I/O pin
Контакт 22 VCC — 5.0 V supply voltage
Контакт 23 GND — Ground reference
Контакт 24 I/O — User I/O pin
Контакт 25 I/O — User I/O pin
Контакт 26 I/O — User I/O pin
Контакт 27 I/O — User I/O pin
Контакт 28 I/O — User I/O pin
Контакт 29 GCLK — Global Clock input
Контакт 30 GCLR — Global Clear input
Контакт 31 I/O — User I/O pin
Контакт 32 I/O — User I/O pin
Контакт 33 I/O — User I/O pin
Контакт 34 OE1 — Output Enable (global)
Контакт 35 I/O — User I/O pin
Контакт 36 I/O — User I/O pin
Контакт 37 GND — Ground reference
Контакт 38 VCC — 5.0 V supply voltage
Контакт 39 I/O — User I/O pin
Контакт 40 I/O — User I/O pin
Контакт 41 I/O — User I/O pin
Контакт 42 I/O — User I/O pin
Контакт 43 I/O — User I/O pin
Контакт 44 I/O — User I/O pin
Контакт 45 OE2 — Output Enable (global)
Контакт 46 I/O — User I/O pin
Контакт 47 I/O — User I/O pin
Контакт 48 I/O — User I/O pin
Контакт 49 I/O — User I/O pin
Контакт 50 I/O — User I/O pin
Контакт 51 VCC — 5.0 V supply voltage
Контакт 52 GND — Ground reference
Контакт 53 I/O — User I/O pin
Контакт 54 I/O — User I/O pin
Контакт 55 I/O — User I/O pin
Контакт 56 I/O — User I/O pin
Контакт 57 I/O — User I/O pin
Контакт 58 I/O — User I/O pin
Контакт 59 I/O — User I/O pin
Контакт 60 I/O — User I/O pin
Контакт 61 I/O — User I/O pin
Контакт 62 I/O — User I/O pin
Контакт 63 I/O — User I/O pin
Контакт 64 TDI — JTAG Test Data In
Контакт 65 I/O — User I/O pin
Контакт 66 I/O — User I/O pin
Контакт 67 I/O — User I/O pin
Контакт 68 I/O — User I/O pin
Контакт 69 I/O — User I/O pin
Контакт 70 VCC — 5.0 V supply voltage
Контакт 71 I/O — User I/O pin
Контакт 72 I/O — User I/O pin
Контакт 73 I/O — User I/O pin
Контакт 74 I/O — User I/O pin
Контакт 75 I/O — User I/O pin
Контакт 76 I/O — User I/O pin
Контакт 77 TDO — JTAG Test Data Out
Контакт 78 I/O — User I/O pin
Контакт 79 I/O — User I/O pin
Контакт 80 I/O — User I/O pin
Контакт 81 I/O — User I/O pin
Контакт 82 I/O — User I/O pin
Контакт 83 GND — Ground reference
Контакт 84 I/O — User I/O pin

Типичное применение

EPM9320ALC84-10N подходит для 6 применениеs: Legacy Industrial Control Boards, Telecom Line-Card Glue Logic, Address Decoding and Chip-Select Generation, Peripheral Bus Interfacing (ISA / PCI / VME), Motor-Control State Machines, Retrofit and Repair of Legacy Equipment.

🏭

Legacy Industrial Control Boards

The EPM9320ALC84-10N is widely deployed in legacy industrial control boards where its 320 macrocells and 60 I/O pins provide ample capacity for PLC-style glue logic, sensor multiplexing, and actuator control sequencing. With a deterministic 10 ns tPD and 5 V I/O tolerance, it directly interfaces to 5 V TTL/CMOS peripherals, encoder inputs, and opto-isolated feedback lines without level shifters. The 84-PLCC socketed package allows field-replacement on existing backplanes, minimizing downtime for retrofit programs in factory automation lines that have been in service for 15-20 years or longer.

🌐

Telecom Line-Card Glue Logic

In telecom line-card and central-office equipment, the EPM9320ALC84-10N serves as deterministic glue logic between framer ICs, TDM switches, and backplane transceivers. Its 144.9 MHz fCNT supports 8 kHz/16 kHz/32 kHz time-slot framing alongside higher-speed E1/T1 clock recovery schemes, while the predictable PIA-based interconnect ensures zero-jitter output timing critical for PDH and SDH tributaries. The JTAG interface enables board-level boundary-scan testing during manufacture and field diagnostics, satisfying the IEEE 1149.1 testability mandates common in telecom-grade hardware. Obsolescence remains a key concern, so redesign programs target MAX II/MAX V equivalents.

🖥️

Address Decoding and Chip-Select Generation

The EPM9320ALC84-10N is ideally suited for memory and peripheral address decoding on legacy microprocessor boards, generating chip-select signals for SRAM, ROM, and I/O peripherals from a wide address bus. With 10 ns tPD, it produces clean chip-select pulses well within one clock cycle of 25-50 MHz 80x86, 68k, or PowerPC host buses. The 320 macrocells comfortably handle 16-to-24-bit address decoding with multiple active-low and active-high outputs, and the in-system programmability lets engineers iterate decoder maps during prototype without re-spinning the PCB. This application is one of the most common uses for the MAX 9000 family.

🔧

Peripheral Bus Interfacing (ISA / PCI / VME)

The EPM9320ALC84-10N acts as a bus-interface bridge between legacy ISA, VME, and simple PCI target peripherals. It implements bus-state decoders, hand-shake sequencers, and interrupt controllers with deterministic 10 ns response, eliminating wait-state unpredictability from discrete TTL logic. The 5 V tolerant I/O connects directly to bus transceivers, while 60 user I/O pins handle address, data steering, and control signal multiplexing. The 84-PLCC socket allows engineers to swap parts for speed-grade upgrades or logic revisions during board bring-up without reworking the PCB.

🏭

Motor-Control State Machines

The EPM9320ALC84-10N implements multi-axis stepper and BLDC motor control state machines by sequencing PWM generators, decoding Hall-sensor or quadrature-encoder feedback, and arbitrating direction/inhibit signals. The 10 ns tPD enables sub-microsecond control-loop updates at 50-100 kHz PWM rates, and the 60 user I/O pins handle multiple axes (typically 3-4 steppers or 2 BLDC motors) from a single device. EEPROM-based configuration retains state machine tables across power cycles, and the JTAG interface supports in-circuit debugging via Altera MAX+PLUS II or Quartus signal-tap logic.

✈️

Retrofit and Repair of Legacy Equipment

The EPM9320ALC84-10N is primarily sourced today to repair and extend the service life of legacy equipment originally designed in the late 1990s and early 2000s. Medical imaging systems, military radios, industrial CNC controllers, and avionics subsystems all depend on the MAX 9000 family's reliability and 5 V tolerance. The PLCC socket mounting is critical here - it allows technicians to swap parts without specialized rework tools, even in field-deployed units. Authorized obsolete-part brokers maintain traceability documentation (date code, lot, original manufacturer) required by aerospace and medical OEM service contracts.

What is the maximum operating frequency of the EPM9320ALC84-10N?
The EPM9320ALC84-10N supports a maximum internal counter frequency (fCNT) of 144.9 MHz with a 10 ns pin-to-pin propagation delay, according to the MAX 9000 family datasheet. The -10 speed grade typically delivers 100 MHz toggle performance on fast I/O pins. This frequency is sufficient for moderate-speed state machines, address decoders, and bus-interface glue logic in 5 V systems.
How many macrocells and user I/O does the EPM9320ALC84-10N have?
The EPM9320ALC84-10N contains 320 macrocells distributed across 16 Logic Array Blocks (LABs) and provides 60 user I/O pins on the 84-pin PLCC package. The remaining pins are dedicated to VCC, GND, JTAG (TMS, TCK, TDI, TDO), and the global clear/clock distribution network. Each macrocell contains a programmable AND/OR array with a flip-flop, supporting both combinatorial and registered logic.
Is the EPM9320ALC84-10N still in production?
According to current distributor listings and the manufacturer catalog, the EPM9320ALC84-10N is marked Obsolete. Inventory is limited to remaining distributor stock and obsolete-component brokers. For new designs, engineers should consider the MAX II, MAX V, or MAX 10 CPLD families as modern replacements, though package and voltage differences may require PCB rework.
What is the difference between EPM9320ALC84-10N and EPM9320LC84-15?
Both parts share the 84-pin PLCC package and 320-macrocell MAX 9000 family architecture. The EPM9320ALC84-10N is the A-suffix (5 V operation) with 10 ns tPD; the EPM9320LC84-15 is the L-suffix (3.3 V operation) with 15 ns tPD. They are NOT drop-in replacements because the core voltage differs. The 10N is also faster, which is why it is preferred when production still allows 5 V rails.
Where can I buy the EPM9320ALC84-10N today?
The EPM9320ALC84-10N is available from obsolete-component distributors and brokers such as Veswin, Xecor, Bettlink, Lisleapex, and Win Source, with reference prices starting around USD 38.50 per unit at qty-1 (as of 2026-09-13). DigiKey and Mouser listings typically show zero stock; sourcing is via independent distributors who specialize in obsolete Altera/Intel parts. Buyers should request traceability documentation.
What is the lead time and stock status for EPM9320ALC84-10N?
As of 2026-09-13, the EPM9320ALC84-10N has no scheduled manufacturing and is sourced exclusively from remaining inventory and broker channels. Lead times vary from immediate shipment (when broker stock is available) to 12-16 weeks when parts must be located through franchise distribution. We recommend requesting multiple quotes and confirming date-code traceability before placing production orders.
Where to download the EPM9320ALC84-10N datasheet PDF?
The official MAX 9000 family datasheet containing EPM9320ALC84-10N specifications can be downloaded from the Intel Programmable Solutions Group website (intel.com/programmable), via the legacy Altera documentation archive, or from third-party distributors such as FPGAkey and FPGAX who host mirrored PDFs. Search for document title 'MAX 9000 Programmable Logic Device Family Data Sheet' published 2008.
What is the pinout configuration of the EPM9320ALC84-10N 84-PLCC?
The EPM9320ALC84-10N in the 84-pin PLCC package uses a J-lead arrangement with pin 1 at the top-left index marker. Pin assignments include four JTAG pins (TMS, TCK, TDI, TDO), a global clear (GCLRn), global clock (GCLK), multiple VCC and GND pins (the MAX 9000 PLCC requires several supply pins to reduce ground bounce), and 60 user I/O pins on the remaining positions. Refer to the MAX 9000 datasheet for the exact I/O-to-pin mapping.
What is the best drop-in replacement for the EPM9320ALC84-10N?
The closest drop-in replacement is the EPM9320ALC84-10 (without the N suffix), which shares the same 84-PLCC package, 320 macrocells, 5 V operation, and 10 ns tPD - the only difference being packaging/tray vs. tape-and-reel. Same-MAX-family variants such as EPM9320ALI84-10 (industrial temp range) also work as pin-compatible substitutes when temperature grade is acceptable. Always verify the temperature grade for the target application.
EPM9320ALC84-10N vs EPM9320ALI84-10 - which should I choose?
Choose EPM9320ALC84-10N (commercial 0C to +70C) for indoor commercial equipment and standard embedded systems. Choose EPM9320ALI84-10 (industrial -40C to +85C) for industrial, outdoor, and harsher environments. Both share the same 84-PLCC package, 320 macrocells, and 10 ns tPD. The Ali variant is more expensive and harder to source, so reserve it for designs where the extended temperature range is genuinely required.
Is there a cross-brand equivalent to the EPM9320ALC84-10N?
Direct cross-brand equivalents to the MAX 9000 family are limited because this CPLD family is proprietary to Altera/Intel. For new designs, modern alternatives include Lattice Semiconductor's ispMACH 4000 family (e.g., LC4256B, LC4384) in equivalent densities, Xilinx CoolRunner-II (e.g., XC2C256, XC2C384), and Microchip (Atmel/Microsemi) ATF1500/ATF2500 CPLDs. These are NOT drop-in and require PCB redesign, but offer functional similarity for glue-logic applications.
What is the price of the EPM9320ALC84-10N?
The EPM9320ALC84-10N reference price is approximately USD 38.50 per unit at quantity 1, USD 34.20 at qty 10, USD 28.95 at qty 100, USD 24.60 at qty 500, and USD 21.40 at qty 1000 (as of 2026-09-13). Prices fluctuate due to scarcity; quotes from multiple obsolete-part distributors typically yield a 15-30% spread. Broker pricing may include date-code premiums for recent inventory.
What programming tools support the EPM9320ALC84-10N?
The EPM9320ALC84-10N is programmed via JTAG using the Altera ByteBlasterMV, ByteBlaster II, or USB-Blaster cables, together with the legacy Altera MAX+PLUS II or Quartus II design software (versions 13.0 and earlier). Modern Quartus Prime still supports MAX 9000 device compilation in legacy mode. For board-level programming, the JTAG chain follows the IEEE 1149.1 standard with TMS, TCK, TDI, TDO, and optional TRST.
Can the EPM9320ALC84-10N operate at 3.3 V instead of 5 V?
No, the EPM9320ALC84-10N (A-suffix) requires 5.0 V VCC operation and is NOT 3.3 V tolerant. For 3.3 V designs, use the L-suffix MAX 9000 parts such as EPM9320LC84-15, EPM9320LC84-20, or EPM9320LI84-20. Mixing 5 V and 3.3 V MAX 9000 parts on the same JTAG chain is acceptable as long as each device's VCC pin is supplied at its rated voltage and the JTAG signal levels are compatible with the lowest VCC in the chain.
What are the key specifications of EPM9320ALC84-10N that engineers should know?
Key specifications: 320 macrocells, 6,000 gates, 60 user I/O, 84-pin PLCC package, 10 ns pin-to-pin delay, 144.9 MHz internal frequency, 5.0 V VCC, commercial 0C to +70C operating range, EEPROM in-system programmability, JTAG IEEE 1149.1 configuration interface, and obsolete lifecycle status. The MAX 9000 family uses a Programmable Interconnect Array (PIA) for deterministic signal routing with predictable timing, making it suitable for hard-real-time control logic.

Справочные инженерные данные для EPM9320ALC84-10N — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the EPM9320ALC84-10N when you need a 5 V tolerant, 320-macrocell MAX 9000 CPLD in the 84-PLCC package for commercial-temperature legacy equipment, telecom line cards, or industrial control boards. For harsh-environment deployments, choose EPM9320ALI84-10 (industrial -40C to +85C, identical footprint). For 3.3 V systems with relaxed timing, choose EPM9320LC84-15 (15 ns tPD). The EPM9320ALC84-10 (tray variant) is functionally identical to the -10N and is a direct alternate when tape-and-reel inventory is unavailable. All variants share the same 84-PLCC footprint, enabling one PCB layout across the entire MAX 9320 PLCC family. Note that all five candidates are obsolete; new designs should consider MAX II or MAX V CPLDs with appropriate footprint adapters.

Сравнение с аналогами

Параметр Этот товар EPM9320ALC84-10 EPM9320ALI84-10 EPM9320LC84-15 EPM9320LC84-20
Package 84-PLCC 84-PLCC - same 84-PLCC - same 84-PLCC - same 84-PLCC - same
Brand Intel (Altera) Intel (Altera) Intel (Altera) Intel (Altera) Intel (Altera)
Macrocells 320 320 320 320 320
Supply Voltage (VCC) 5.0 V 5.0 V 5.0 V 3.3 V 3.3 V
Pin-to-Pin Delay (tPD) 10 ns 10 ns 10 ns 15 ns 20 ns
Operating Temperature 0C to +70C (Commercial) 0C to +70C (Commercial) -40C to +85C (Industrial) 0C to +70C (Commercial) 0C to +70C (Commercial)
User I/O 60 60 60 60 60
Lifecycle Status Obsolete Obsolete Obsolete Obsolete Obsolete

Ключевые отличия

  • Industrial temperature variant available in same package (против EPM9320ALI84-10)
  • 3.3 V variant enables mixed-voltage system integration (против EPM9320LC84-15)
  • Identical die in alternative packaging (против EPM9320ALC84-10)

Заметки по проектированию

The EPM9320ALC84-10N requires a stable 5.0 V VCC supply with a tolerance of +/-5% (4.75 V to 5.25 V). Place a 0.1 uF decoupling capacitor within 50 mils of each VCC pin (the 84-PLCC has multiple VCC and GND pins distributed around the package) to minimize ground bounce and VCC sag during simultaneous switching of high-fanout outputs. Bulk decoupling of 10-47 uF tantalum or aluminum polymer is recommended at the board-level power entry to the device's VCC rail.

The 84-PLCC package is a through-hole socket-mount part. Use a high-quality machined-pin PLCC socket (3M, Mill-Max, or equivalent) rated for the operating temperature range, especially for industrial and military designs. Avoid low-cost stamped sockets which may lose contact after thermal cycling. The PLCC socket footprint must accommodate the J-lead geometry - refer to the JEDEC MO-047 package outline for recommended land pattern dimensions.

Do not confuse the A-suffix (5 V VCC) EPM9320ALC84-10N with the L-suffix (3.3 V VCC) EPM9320LC84-15/20. Applying 5 V to a 3.3 V L-variant will permanently damage the device. The 'A' and 'L' letters in the Altera MAX 9000 nomenclature encode the voltage class, and engineers upgrading or downgrading designs must verify both the voltage and speed-grade suffixes. The 'N' suffix indicates tape-and-reel packaging versus tray.

Route JTAG signals (TMS, TCK, TDI, TDO) as short, parallel traces with a ground return path to avoid crosstalk. Place a 10 kohm pull-up on TCK and TMS to prevent floating inputs that may inadvertently trigger JTAG state-machine transitions. If the device is part of a multi-device JTAG chain, include 4.7 kohm series termination resistors on TDI/TDO between adjacent devices to dampen reflections on longer chains (>6 inches).

Информация о соответствии

RoHS
Non Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Без свинца
No
Без галогенов
Unknown
Конфликтные минералы
Compliant

MAX 9000 family parts from this generation typically use tin-lead (SnPb) PLCC leads and are not RoHS-compliant. Lead-free variants carry the 'N' or other suffix. For new RoHS-compliant designs, modern MAX II/MAX V/MAX 10 CPLD families should be evaluated.

Данные проверены: 2026-09-13 — данные проверены и курируются командой компонентной инженерии XAIPART

Похожие запросы

EPM9320ALC84-10N EPM9320ALC84-10N datasheet EPM9320ALC84-10N pinout MAX 9000 CPLD 320 macrocell Altera EPM9320ALC84-10N 84-PLCC CPLD obsolete EPM9320ALC84-10N vs EPM9320ALI84-10 EPM9320ALC84-10N drop-in replacement buy EPM9320ALC84-10N EPM9320ALC84-10N price MAX 9000A 5V CPLD legacy where to download EPM9320ALC84-10N datasheet PDF EPM9320ALC84-10N JTAG programming

Связанные компоненты & термины

Intel Altera EPM9320ALC84-10N EPM9320ALC84-10 EPM9320ALI84-10 EPM9320LC84-15 EPM9320LC84-20 EPM9320LI84-20 MAX 9000 MAX 9000A CPLD Complex Programmable Logic Device macrocell PLCC-84 Plastic Leaded Chip Carrier JTAG IEEE 1149.1 EEPROM ByteBlaster Quartus II MAX+PLUS II Programmable Interconnect Array PIA altera MAX architecture 5V TTL logic address decoder glue logic
Быстрый запрос цены (RFQ)
Заполните все данные — наша команда продаж ответит в течение 24 часов
Артикул Производитель Корпус QTY Целевая цена Итого
Итого: $0.00 USD
✓
Запрос цены отправлен!

Мы ответим на ваш email в течение 24 часов

1
RFQ отправлен
2
Предложение получено
3
Заказ оформлен
4
Оплата
5
Отправлено
6
Доставлено
Просмотреть детали RFQ