EP1810GM883B vs EP1810JC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GM883B sa pamamagitan ng Altera at EP1810JC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810GM883B EP1810JC-25
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Device Family EP1810 (Classic EPLD) —
Macrocells 48 48
User Flip-Flops Up to 64 —
Total Inputs 60 —
Dedicated Inputs 12 12
I/O Pins 48 (bidirectional, tri-state) —
Propagation Delay (tPD) 50 ns max 25 ns
Supply Voltage (VCC) 4.5 V to 5.5 V 4.75 V to 5.25 V
Technology CMOS, UV-erasable CMOS, UV-erasable (windowed ceramic DIP)
Temperature na Operasyon -55 °C to +125 °C (Military, MIL-STD-883B) -40 °C to 85 °C (industrial, per distributor listings)
Package Type Ceramic Pin Grid Array (PGA), 84 pins —
Package Designator GM (ceramic PGA) —
Processing Level MIL-STD-883B (Class B) —
Programming Method UV-erasable / Altera programming hardware —
Uri ng Pagpapasok Through-hole (PGA socket or PCB through-hole) Through-hole
Lead-Free / RoHS [DATA_NEEDED: lead-free status] —
Logic Family TTL-compatible I/O —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — Altera/Intel Classic EPLD (EP1810 series)
Maximum Toggle Frequency — [DATA_NEEDED: max fMAX]
Input Lines — 60 (including I/O)
I/O Lines — 48
External Clock Inputs — 4
Packhaging — 28-pin ceramic DIP (J) with quartz window
Erasure Method — UV light (windowed package)
Tindminan RoHS — [DATA_NEEDED: RoHS compliance status]
Katayuan ng Lifecycle — NRND (Not Recommended for New Designs)

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