EP1810GM883B vs EP1810JC-25 比較
詳細並排比較 EP1810GM883B 由 Altera 與 EP1810JC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GM883B | EP1810JC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | 48 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | 25 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 4.75 V to 5.25 V |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable (windowed ceramic DIP) |
| 工作溫度 | -55 °C to +125 °C (Military, MIL-STD-883B) | -40 °C to 85 °C (industrial, per distributor listings) |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | — |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| 安裝類型 | Through-hole (PGA socket or PCB through-hole) | Through-hole |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera/Intel Classic EPLD (EP1810 series) |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| External Clock Inputs | — | 4 |
| 封裝 | — | 28-pin ceramic DIP (J) with quartz window |
| Erasure Method | — | UV light (windowed package) |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance status] |
| 生命週期狀態 | — | NRND (Not Recommended for New Designs) |