EP1810JC-35 vs EP1810JI-45 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-35 sa pamamagitan ng Intel at EP1810JI-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JC-35 EP1810JI-45
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family Classic EPLD (EP1810) —
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) UV-Erasable / OTP Complex PLD
Number of Macrocells 48 —
Propagation Delay (tpd) 35 ns (max) —
Maksimum na Taktiko ng Oras [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS —
Supply Voltage (Vcc) 5 V (nominal) —
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) 68-pin JLCC (J-leaded ceramic chip carrier)
Number of Terminals 68 68
Terminal Form J-Bend J BEND
Hanay ng Temperature na Operasyon 0°C to 70°C (Commercial) —
Temperature Grade Commercial INDUSTRIAL
Erasure Method UV (quartz-windowed ceramic package) —
Tindminan RoHS Compliant (per Altera listing) —
Lead-Free Status Lead-free (per distributor listing) —
Uri ng Pagpapasok Surface Mount (J-Lead) —
Logic Architecture Programmable AND/OR array with macrocell outputs —
Manufacturer — Altera (now Intel FPGA)
Series — Classic EPLD Family
Macrocell Count — 48
Maximum Operating Frequency — 33.3 MHz
Propagation Delay (tPD) — 50 ns
Configurable I/O Lines — 48
Dedicated Inputs — 12
Technology — CMOS EPROM
Package Code — QCCJ
Package Shape — SQUARE
Temperature na Operasyon — -40 °C to +85 °C
Volte ng Pagbibigay — 5 V (TTL compatible)
Programming Method — UV-erase (windowed) / OTP via JEDEC

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