EP1810JI-35 vs EP1810LC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-35 sa pamamagitan ng Intel at EP1810LC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JI-35 EP1810LC-25
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family Classic EPLD —
Macrocells 48 48
Logic Array Blocks 8 LABs of 16 macrocells —
Dedicated Inputs 48 12
Pin-to-Pin Propagation Delay (tPD) 35 ns —
Speed Grade -35 —
Packhaging 28-pin JLCC (J-leaded ceramic, windowed) 68-pin JLCC (J-leaded ceramic chip carrier)
Process Technology CMOS EPROM (UV-erasable) —
Temperature na Operasyon -40C to +85C (Industrial) [DATA_NEEDED: temperature grade for LC package]
Volte ng Pagbibigay 5 V (typical classic EPLD) —
Programmability UV-erase, windowed for lab reprogram —
Uri ng Pagpapasok Through-Hole (J-lead) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Level ng MSL [DATA_NEEDED: MSL rating] —
Programming Interface JEDEC fuse file via legacy programmer —
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Propagation Delay (tPD) — 25 ns
I/O Pins — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Technology — CMOS EPLD (erasable programmable logic device)
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Katayuan ng Lifecycle — Obsolete (legacy Altera Classic family)

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