EP1810JI-35 vs EP1810LI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-35 sa pamamagitan ng Intel at EP1810LI-45 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP1810JI-35 | EP1810LI-45 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | — |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Packhaging | 28-pin JLCC (J-leaded ceramic, windowed) | 68-pin PLCC / PQCC68 (J-Lead) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Volte ng Pagbibigay | 5 V (typical classic EPLD) | 5 V |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Uri ng Pagpapasok | Through-Hole (J-lead) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | [DATA_NEEDED: RoHS status] |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic |
| Usable Gates | — | 900 |
| Maximum User I/O | — | 64 inputs / 48 outputs |
| Pin-to-Pin Logic Delay (tPD) | — | 45 ns |
| Counter Frequency (fCNT) | — | up to 100 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Technology | — | CMOS, UV-erasable EPROM configuration |
| Hanay ng Temperature na Operasyon | — | -40 C to +85 C (Industrial, 'I' suffix) |
| Logic Blocks | — | 12 LABs of 4 macrocells each |
| Configuration Memory | — | Non-volatile UV-erasable EPROM |
| Programming Method | — | Altera programming hardware with MAX+PLUS II / legacy tools |
| Manufacturer | — | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) |