EP1810LC-25 vs EP1810LC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-25 sa pamamagitan ng Altera at EP1810LC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LC-25 | EP1810LC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Packhaging | 68-pin JLCC (J-leaded ceramic chip carrier) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Package Code | LC = 68-pin JLCC | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS, low-power (LC) |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| Katayuan ng Lifecycle | Obsolete (legacy Altera Classic family) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | unknown (legacy ceramic package) |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade for LC package] | [DATA_NEEDED: temperature grade] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Volte ng Pagbibigay | — | 5 V (typical) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Bilang ng Pins | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |