EP1810LC-25 vs EP1810LC-30 比較
詳細並排比較 EP1810LC-25 由 Altera 與 EP1810LC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810LC-25 | EP1810LC-30 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| 封裝 | 68-pin JLCC (J-leaded ceramic chip carrier) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Package Code | LC = 68-pin JLCC | — |
| 安裝類型 | Surface Mount | — |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS, low-power (LC) |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| 生命週期狀態 | Obsolete (legacy Altera Classic family) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | unknown (legacy ceramic package) |
| 工作溫度 | [DATA_NEEDED: temperature grade for LC package] | [DATA_NEEDED: temperature grade] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| 供應電壓 | — | 5 V (typical) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| 腳位數 | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |