EP1810LC-30 vs EP1810LC-35T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-30 sa pamamagitan ng Altera at EP1810LC-35T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LC-30 | EP1810LC-35T |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD | — |
| Macrocells | 48 | — |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Volte ng Pagbibigay | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | CMOS |
| Packhaging | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Programming | Device programmer or JTAG | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | 0 C to +70 C (Commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Bilang ng Pins | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| Tindminan RoHS | unknown (legacy ceramic package) | Non-compliant (legacy PLCC product) |
| Device Family | — | EP1810 Classic EPLD |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Logic Compatibility | — | 100% TTL emulation |
| Package Suffix | — | T = Tape and Reel |
| Uri ng Pagpapasok | — | Surface Mount (PLCC socket or direct solder) |
| Programming Method | — | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |