EP3C25F324C6N vs EP3C25F324I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3C25F324C6N sa pamamagitan ng Intel at EP3C25F324I7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3C25F324C6N | EP3C25F324I7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone III | — |
| Family | Cyclone III (low-power, low-cost FPGA) | Cyclone III |
| Logic Elements (LE) | 24,624 | — |
| Total Memory Bits | 608,256 bits | — |
| Embedded Memory Blocks | M9K blocks, 66 total | — |
| Embedded Multipliers | 66 (18x18) | — |
| DSP Blocks | 66 dedicated 18x18 multipliers | — |
| User I/O Pins | 215 | — |
| Number of I/O Banks | 8 | — |
| PLLs | 4 general-purpose PLLs | 4 |
| Packhaging | 324-BGA (FBGA-324), fine-pitch | 324-ball FBGA (Fine-Pitch BGA) |
| Speed Grade | C6 (commercial) | 7 (slower speed grade, lower power) |
| Temperature na Operasyon | 0C to +85C (commercial) | -40C to +100C (Industrial) |
| Process Technology | TSMC 65 nm low-power (LP) | 65 nm |
| Configuration Schemes | Passive Serial, Fast Passive Parallel, JTAG | — |
| Lead-Free / RoHS | Yes (lead-free, RoHS compliant) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Logic Elements (LEs) | — | 24,624 |
| Embedded Memory | — | 608,256 bits (66 M9K blocks of 9 Kbits each) |
| Embedded 18x18 Multipliers | — | 66 |
| Maximum User I/O Pins | — | 215 |
| LVDS Pairs | — | 66 |
| Global Clock Networks | — | 20 |
| Core Voltage | — | 1.2 V |
| I/O Bank Voltage Range | — | 1.2 V to 3.3 V (LVCMOS, LVTTL, LVDS, SSTL, HSTL) |
| Configuration Modes | — | Active Serial (AS), Passive Serial (PS), JTAG, Fast Passive Parallel (FPP) |
| Tindminan RoHS | — | Compliant |
| Lead-Free | — | Yes |
| Level ng MSL | — | 3 (168 hours) |