EP3C80U484C7 vs EP3C55U484C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3C80U484C7 sa pamamagitan ng Intel at EP3C55U484C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3C80U484C7 | EP3C55U484C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone III | Cyclone III |
| Family | EP3C80 | — |
| Logic Elements | 81,264 | — |
| Embedded Memory | 2,810,880 bits (295 M9K blocks) | — |
| Embedded 18x18 Multipliers | 244 | — |
| PLLs | 4 | — |
| Maximum User I/O Pins | 429 (approximate, package-dependent) | 327 |
| Packhaging | 484-FBGA (UBGA) | 484-ball UBGA (Ultra-FineLine BGA) |
| Speed Grade | -7 (commercial) | C7 (Commercial) |
| Core Voltage | 1.2 V | 1.2 V |
| I/O Voltage Range | 1.2 V to 3.3 V | — |
| Process Technology | 65 nm low-power CMOS | 65 nm CMOS |
| Temperature ng Junction na Operasyon | 0 C to 85 C (commercial) | — |
| Configuration Modes | Passive Serial, Active Serial, JTAG, AES-encrypted bitstream | — |
| Memory Interface Support | DDR, DDR2, QDRII SDRAM | — |
| I/O Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL | — |
| Tindminan RoHS | Compliant | Compliant |
| Logic Elements (LEs) | — | 55,856 |
| Logic Array Blocks (LABs) | — | 3,488 |
| Embedded Memory (bits) | — | 2,396,160 |
| Embedded Multipliers (18x18) | — | 156 |
| Number of PLLs | — | 4 |
| Maximum Operating Frequency | — | 437 MHz |
| I/O Bank Voltages | — | 1.2 V / 2.5 V / 3.0 V / 3.3 V |
| Package Dimensions | — | 19 x 19 mm |
| Ball Pitch | — | 0.80 mm |
| Temperature na Operasyon | — | 0C to +85C (Commercial) |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |