EP3SE50F484C3G vs EP3SE50F484C2G Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE50F484C3G sa pamamagitan ng Intel at EP3SE50F484C2G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Intel
EP3SE50F484C2G EP3SE50F484C2G - Stratix III E FPGA 47.5K LE 484-FBGA | Intel

EP3SE50F484C2G - Stratix III E FPGA 47.5K LE 484-FBGA | Intel

EP3SE50F484C2G ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP3SE50F484C3G EP3SE50F484C2G
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Huling Pagbili
Family Stratix III E —
Logic Elements 47,500 —
Adaptive Logic Modules (ALMs) 19,000 —
Total Embedded Memory 5,760,000 bits (5.76 Mbit) —
M9K Memory Blocks 320 (2,304 Kbits) —
M144K Memory Blocks 12 (1,728 Kbits) —
User I/O Pins 296 —
18x18 Multipliers 384 —
PLLs 4 —
Global Clock Networks 16 —
Packhaging 484-ball FCBGA (F484), 1.0 mm pitch —
Speed Grade C3 —
Temperature na Operasyon 0C to +85C (commercial, "C") 0 °C to +85 °C (TJ)
Process Node 65 nm TSMC low-power —
Core Voltage 1.1 V —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS Compliant (lead-free) Compliant
Series — Stratix III E
Number of Logic Elements / Cells — 47,500
Number of LABs / CLBs — 1,900
Total RAM Bits — 5,760,000 (5,760 Kbit)
Number of User I/O — 296
Packhaging / Kaso — 484-BBGA, FCBGA (FineLine BGA)
Core Voltage Supply — 0.86 V to 1.15 V
Process Technology — 40 nm TSMC low-power CMOS
Logic Element Architecture — Adaptive Logic Module (ALM) with 8-input fracturable LUT
Embedded DSP Blocks — Yes (variable-precision multipliers)
Transceivers — Multi-gigabit transceivers (selected package pins)
Memory Interface Support — DDR / DDR2 / DDR3 with hard PHY
Partial Reconfiguration — Supported
Configuration Interface — JTAG, Passive Serial, Fast Passive Parallel
Part Status — Active (Intel catalogue); long-term supply subject to Stratix III lifecycle policy

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