EP610PC-30 vs EP610PC-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-30 sa pamamagitan ng Altera at EP610PC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610PC-30 EP610PC-20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Device Family Classic EPLD (EP610) —
Macrocells 16 —
Usable Gates 300 300
Propagation Delay (tPD) 30 ns 20 ns
Maximum Pipeline Frequency 33.3 MHz (typical) / 100 MHz pipelined —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V ±10%
Process Technology CMOS EPROM CMOS EPROM
Packhaging 24-pin PDIP (0.300 inch) PDIP-24
Uri ng Pagpapasok Through-Hole —
Programmability One-Time Programmable (OTP, no window on plastic PDIP) —
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (commercial)
Output Drive Current [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] —
Input Pins (Dedicated) [DATA_NEEDED: dedicated input count from datasheet pinout] —
I/O Pins [DATA_NEEDED: bidirectional I/O count from datasheet pinout] —
Programming Tool Altera A+PLUS / MAX+PLUS II (legacy) —
Tindminan RoHS Not applicable (legacy non-compliant package per distributor listing) Non-compliant (legacy PDIP)
Lead Free Status Not applicable —
Current Distributor Rochester Electronics, LLC (authorized continuing source) —
Family — Classic EPLD
Logic Elements — 16 macrocells
Maximum Operating Frequency — 100 MHz (pipelined)
Bilang ng Pins — 24
Programmable Flip-Flops — 16
Input Pins — 24
Output Pins — 16
I/O Compatibility — TTL
Program/Erase Method — UV (windowed) or OTP

Mga Datasheets at Resources

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