EP610PC-30 vs EP610PC-20 比較
詳細並排比較 EP610PC-30 由 Altera 與 EP610PC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-30 | EP610PC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Family | Classic EPLD (EP610) | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 20 ns |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V ±10% |
| Process Technology | CMOS EPROM | CMOS EPROM |
| 封裝 | 24-pin PDIP (0.300 inch) | PDIP-24 |
| 安裝類型 | Through-Hole | — |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Output Drive Current | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] | — |
| Input Pins (Dedicated) | [DATA_NEEDED: dedicated input count from datasheet pinout] | — |
| I/O Pins | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] | — |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) | — |
| RoHS 狀態 | Not applicable (legacy non-compliant package per distributor listing) | Non-compliant (legacy PDIP) |
| Lead Free Status | Not applicable | — |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) | — |
| Family | — | Classic EPLD |
| Logic Elements | — | 16 macrocells |
| Maximum Operating Frequency | — | 100 MHz (pipelined) |
| 腳位數 | — | 24 |
| Programmable Flip-Flops | — | 16 |
| Input Pins | — | 24 |
| Output Pins | — | 16 |
| I/O Compatibility | — | TTL |
| Program/Erase Method | — | UV (windowed) or OTP |