EP910DC-35 vs EP910DC-40 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-35 sa pamamagitan ng Altera at EP910DC-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DC-35 EP910DC-40
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Type UV-Erasable CMOS PLD (PAL-type) —
Family Classic EPLD EP910 —
Architecture PAL-type sum-of-products AND-OR array PAL-type AND/OR, UV-erasable CMOS
Usable Gates 900 gates —
Macrocells 24 24
Product Terms 240 240 maximum
Dedicated Inputs 12 12
I/O Pins 24 —
Total Inputs 36 —
Propagation Delay (tpd) 35 ns —
Maksimum na Taktiko ng Oras 37 MHz (typical, internal) —
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) —
Temperature na Operasyon 0 °C to +70 °C (commercial) —
Packhaging 40-pin CDIP (Ceramic DIP) with quartz window DIP-40 (ceramic, through-hole)
Lead Pitch 2.540 mm —
Termination Style Through-Hole —
Programming Method JEDEC fuse map via device programmer; UV erase UV-erase + EPROM programmer; on-board logic test circuitry
Technology CMOS, UV-erasable EPROM cell —
Tindminan RoHS Non-compliant (ceramic DIP with Pb-bearing lead finish) [DATA_NEEDED: rohs_status]
Lifecycle Obsolete / last-time-buy from authorized distributors —
Device Family — Classic EPLD (EP910 series)
Bidirectional I/O Pins — 24
Total Inputs to Logic Array — 36
Maximum Propagation Delay (tPD) — 40 ns
Maximum Operating Frequency (fMAX) — 25 MHz
Global Clocks — 2
Volte ng Pagbibigay — 5 V (typical for Classic EPLD family)
Operating Temperature (Commercial) — 0 °C to 70 °C
Uri ng Pagpapasok — Through-Hole

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita