EP910DC-35 vs EP910DI-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-35 sa pamamagitan ng Altera at EP910DI-30 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndPagsanggunian na paghahambing
| Parametro | EP910DC-35 | EP910DI-30 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | — |
| Family | Classic EPLD EP910 | Classic EPLD (Altera EP910 series) |
| Architecture | PAL-type sum-of-products AND-OR array | — |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | — |
| Product Terms | 240 | — |
| Dedicated Inputs | 12 | 10 |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | 30 ns |
| Maksimum na Taktiko ng Oras | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | -40C to +85C (industrial) |
| Packhaging | 40-pin CDIP (Ceramic DIP) with quartz window | CDIP-40 (ceramic DIP, 40-pin with UV window) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | — |
| Technology | CMOS, UV-erasable EPROM cell | CMOS, UV-erasable EPROM |
| Tindminan RoHS | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS compliance status] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Product Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Macrocell Count | — | 24 |
| Maximum Toggle Frequency (fmax) | — | 62 MHz |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |
| Dedicated I/O Pins | — | 12 (12 input + 12 output) |
| Output Enable Pins | — | 2 |
| Bilang ng Pin | — | 40 |
| Programmable Logic Element | — | JEDEC fuse map (3rd-party programmer) |
| Manufacturer (Original) | — | Altera (now Intel PSG) |
| Current Distributor / Authorized Aftermarket | — | Rochester Electronics, LLC |