EP910ILC-12 vs EP910ILC-15N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-12 sa pamamagitan ng Intel at EP910ILC-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910ILC-12 EP910ILC-15N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Family Altera EP910 Classic EPLD Classic
Number of Macrocells 24 —
Usable Gates 450 (typical) —
Propagation Delay (tPD) 12 ns (max) —
Supply Voltage (VCC) 4.75 V to 5.25 V 4.75 V to 5.25 V (5 V nominal)
Nominal Supply 5 V —
Memory Technology UV-erasable CMOS EPROM —
Packhaging 28-PLCC (J-Lead, 11.5 x 11.5 mm) PLCC-44 (J-lead, surface mount)
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon -40 °C to +85 °C (industrial grade, 'I' suffix) 0 C to +70 C (commercial)
Configuration Storage Non-volatile EPROM (instant-on) —
Programming Method Altera programming algorithm (serial/parallel master-slave) —
Level ng MSL [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: RoHS status] Compliant
Bilang ng Pins 28 —
Feedback Paths 16 dedicated —
Logic Gates — 450
Macro Cells — 24
Maximum Propagation Delay (tPD) — 15 ns
Maximum Operating Frequency — 66.6 MHz
User I/O Pins — 36
Dedicated Input Pins — 16
Process Technology — CMOS EPROM (one-time programmable)
JTAG Support — IEEE 1149.1 boundary-scan
Programming — EPROM / JTAG (Classic EP-series)

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