EP910LI-40T vs EP910LC-40T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-40T sa pamamagitan ng Intel at EP910LC-40T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-40T | EP910LC-40T |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable |
| Volte ng Pagbibigay | 5 V (typical) | 5 V (4.75 V to 5.25 V) |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40 C to +85 C (commercial, per -LC suffix family) |
| Architecture | PAL-type with global bus | — |
| Packhaging | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | PLCC-44 (PQCC44) |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - not stated in web data] |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Equivalent Gates | — | 450 gates |
| Logic Array Blocks | — | 4 Logic Expandable AND-OR arrays |
| User I/O Pins | — | 36 |
| Maximum Frequency (fMAX) | — | 25 MHz |
| Programming | — | Altera MAX+PLUS II / APLUS tools |
| Erase/Reprogram Cycles | — | 100 (windowed UV-erase family) |
| Bilang ng Pin | — | 44 |
| Packaging Option | — | Tape and Reel (T suffix) |