EP910LI-40T vs EP910LC-40T 比較
詳細並排比較 EP910LI-40T 由 Intel 與 EP910LC-40T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-40T | EP910LC-40T |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable |
| 供應電壓 | 5 V (typical) | 5 V (4.75 V to 5.25 V) |
| 工作溫度 | -40C to +85C (Industrial) | -40 C to +85 C (commercial, per -LC suffix family) |
| Architecture | PAL-type with global bus | — |
| 封裝 | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | PLCC-44 (PQCC44) |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - not stated in web data] |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Equivalent Gates | — | 450 gates |
| Logic Array Blocks | — | 4 Logic Expandable AND-OR arrays |
| User I/O Pins | — | 36 |
| Maximum Frequency (fMAX) | — | 25 MHz |
| Programming | — | Altera MAX+PLUS II / APLUS tools |
| Erase/Reprogram Cycles | — | 100 (windowed UV-erase family) |
| 腳位數 | — | 44 |
| Packaging Option | — | Tape and Reel (T suffix) |