EPC22C20N vs EPC21LC20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC22C20N sa pamamagitan ng Altera at EPC21LC20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPC21LC20 - Altera 2 Mb Config PROM for SRAM-based LUT Devices | PLCC-20
EPC21LC20 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPC22C20N | EPC21LC20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | Configuration PROM for SRAM-based LUT FPGAs | — |
| Target FPGA Family | FLEX 10K, FLEX 6000, APEX 20K series | — |
| Configuration Interface | Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | IEEE 1149.1 (JTAG) |
| Volte ng Pagbibigay | 3.3 V or 5 V | — |
| Packhaging | 20-pin PLCC (J-lead) | — |
| Package Marking Code | EPC22C20N | — |
| Bilang ng Pin | 20 | — |
| Uri ng Pagpapasok | Surface Mount / Socket | Surface Mount (PLCC socket or solder) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Bitstream Capacity | [DATA_NEEDED: bitstream capacity in bits] | — |
| Configuration Time | [DATA_NEEDED: typical configuration time] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm from Altera product page] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Katayuan ng Lifecycle | Obsolete (last-time-buy from Altera announced for legacy configuration devices) | — |
| Uri ng Memory | — | Serial Configuration PROM (Flash-based, in-system programmable) |
| Density | — | 2 Mb (2,097,152 bits) |
| Configuration Mode Supported | — | Serial (PS) for Altera SRAM-based LUT FPGAs |
| Maximum DCLK Frequency | — | 10 MHz |
| Access Time | — | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] |
| Program/Erase Endurance | — | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] |
| Operating Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Standby Current | — | [DATA_NEEDED: ICCSB value] |
| Active Read Current | — | [DATA_NEEDED: ICC active current] |
| Operating Temperature (commercial) | — | 0 °C to +70 °C (LC suffix) |
| Operating Temperature (industrial) | — | [DATA_NEEDED: -40 to +85 °C for LI variant] |
| Packhaging / Kaso | — | 20-pin PLCC (J-lead, JEDEC MS-018) |
| Level ng MSL | — | [DATA_NEEDED: confirm moisture sensitivity level] |
| Lead-Free (Pb-free) | — | [DATA_NEEDED: confirm] |
| Compatible FPGA Families | — | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) |
| JTAG Boundary-Scan Compliant | — | Yes (IEEE Std 1149.1) |
| Data Width | — | 1 bit (serial DATA output) |