EPC22C20N vs EPC21LC20 比較
詳細並排比較 EPC22C20N 由 Altera 與 EPC21LC20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC22C20N | EPC21LC20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | 啟用中 |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | Configuration PROM for SRAM-based LUT FPGAs | — |
| Target FPGA Family | FLEX 10K, FLEX 6000, APEX 20K series | — |
| Configuration Interface | Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | IEEE 1149.1 (JTAG) |
| 供應電壓 | 3.3 V or 5 V | — |
| 封裝 | 20-pin PLCC (J-lead) | — |
| Package Marking Code | EPC22C20N | — |
| 腳位數 | 20 | — |
| 安裝類型 | Surface Mount / Socket | Surface Mount (PLCC socket or solder) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| Bitstream Capacity | [DATA_NEEDED: bitstream capacity in bits] | — |
| Configuration Time | [DATA_NEEDED: typical configuration time] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm from Altera product page] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| 生命週期狀態 | Obsolete (last-time-buy from Altera announced for legacy configuration devices) | — |
| 記憶體類型 | — | Serial Configuration PROM (Flash-based, in-system programmable) |
| Density | — | 2 Mb (2,097,152 bits) |
| Configuration Mode Supported | — | Serial (PS) for Altera SRAM-based LUT FPGAs |
| Maximum DCLK Frequency | — | 10 MHz |
| Access Time | — | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] |
| Program/Erase Endurance | — | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] |
| Operating Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Standby Current | — | [DATA_NEEDED: ICCSB value] |
| Active Read Current | — | [DATA_NEEDED: ICC active current] |
| Operating Temperature (commercial) | — | 0 °C to +70 °C (LC suffix) |
| Operating Temperature (industrial) | — | [DATA_NEEDED: -40 to +85 °C for LI variant] |
| 封裝 / 外殼 | — | 20-pin PLCC (J-lead, JEDEC MS-018) |
| MSL 等級 | — | [DATA_NEEDED: confirm moisture sensitivity level] |
| Lead-Free (Pb-free) | — | [DATA_NEEDED: confirm] |
| Compatible FPGA Families | — | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) |
| JTAG Boundary-Scan Compliant | — | Yes (IEEE Std 1149.1) |
| Data Width | — | 1 bit (serial DATA output) |