EPC2L20 vs EPC2LC20CAD Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC2L20 sa pamamagitan ng Altera at EPC2LC20CAD sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC2L20 EPC2LC20CAD
Brand Altera Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle Obsolete Obsolete
Uri ng Memory Configuration PROM (non-volatile) Configuration PROM (Flash)
Laki ng Memory 1.6 Mbit —
Organisasyon 8-bit byte —
Interface Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) —
Programmability In-system programmable via JTAG —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (VCCSEL selectable) —
Cascade Support Yes - multi-device daisy chain —
Boundary Scan JTAG IEEE 1149.1 BST —
Packhaging 20-pin PLCC (J-lead) 20-pin J-lead PLCC (PLCC-20)
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Surface Mount / Through-hole (PLCC socket)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -40C to +85C (commercial)
Level ng MSL [DATA_NEEDED: MSL rating] —
Tindminan RoHS RoHS Compliant (per IC Components listing) Compliant
Process Technology Low-power CMOS —
Target FPGAs APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix —
Memory Capacity — 1.6 Mbit
Volte ng Pagbibigay — 3.3 V (nominal)
I/O Voltage Tolerance — 5 V tolerant
Configuration Mode — Serial (bit-wide, Altera FPGAs)
Program Interface — IEEE Std 1149.1 JTAG (in-system programmable)
Bilang ng Pin — 20
Maximum Input Voltage (DC) — -0.3 V to +7.0 V
Input Undershoot/Overshoot — -2.0 V to +7.0 V for <100 mA, <20 ns no-load
Compatible FPGA Families — APEX 20K, ACEX 1K, Cyclone, Stratix
Programming Method — JTAG ISP (no external programmer required)

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