EPC2T32U vs EPC2T32N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC2T32U sa pamamagitan ng Altera at EPC2T32N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC2T32U EPC2T32N
Brand Altera Altera
Kategorya Memory ICs FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Fungsi Configuration PROM for SRAM-based LUT FPGAs —
Memory Density 1.6 Mbit —
Volte ng Pagbibigay 3.3 V or 5.0 V (user-selectable) —
Programmability In-system programmable via JTAG (IEEE 1149.1) —
Configuration Modes Supported Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG —
Packhaging 32-pin TQFP 32-TQFP (7x7 mm)
Temperature na Operasyon Commercial / Industrial grade [DATA_NEEDED: exact range] 0 C to +70 C
Cascading Support Yes, via dedicated cascade port for density expansion —
Compression Support Altera bitstream decompression (up to 50% storage reduction) —
Compatible FPGA Families APEX II, APEX 20K, Mercury, ACEX 1K —
Lead-Free Finish Yes (per part suffix 'U') —
Uri ng Pagpapasok Surface Mount Surface Mount
Level ng MSL [DATA_NEEDED: MSL rating] —
Tindminan RoHS Compliant Compliant (lead-free)
Hand-shake Pins nSTATUS, nCONFIG, CONF_DONE —
Laki ng Memory — 1.6 Mbit
Programmable Type — In System Programmable (Flash)
Configuration Mode — Passive Serial (PS) / JTAG ISP
Maksimum na Taktiko ng Oras — 10 MHz
Supply Voltage - VCCINT — 3.0 V to 3.6 V / 4.75 V to 5.25 V (dual supply)
Interface — Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE)
JTAG Compliance — IEEE 1149.1 (boundary-scan, ISP)
Bilang ng Pin — 32
Sector Architecture — Flash with built-in CRC
Cascade Support — Yes (multi-device daisy-chain)
CONF_DONE / nSTATUS Drive — Open-drain

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