EPC2T32U vs EPC2T32N 对比

详细并排对比 EPC2T32U 出自 Altera 和 EPC2T32N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC2T32U EPC2T32N
品牌 Altera Altera
分类 Memory ICs FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $16.10 $6.95
功能 Configuration PROM for SRAM-based LUT FPGAs —
Memory Density 1.6 Mbit —
电源电压 3.3 V or 5.0 V (user-selectable) —
Programmability In-system programmable via JTAG (IEEE 1149.1) —
Configuration Modes Supported Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG —
封装 32-pin TQFP 32-TQFP (7x7 mm)
工作温度 Commercial / Industrial grade [DATA_NEEDED: exact range] 0 C to +70 C
Cascading Support Yes, via dedicated cascade port for density expansion —
Compression Support Altera bitstream decompression (up to 50% storage reduction) —
Compatible FPGA Families APEX II, APEX 20K, Mercury, ACEX 1K —
Lead-Free Finish Yes (per part suffix 'U') —
安装类型 Surface Mount Surface Mount
MSL 等级 [DATA_NEEDED: MSL rating] —
RoHS 状态 Compliant Compliant (lead-free)
Hand-shake Pins nSTATUS, nCONFIG, CONF_DONE —
存储容量 — 1.6 Mbit
Programmable Type — In System Programmable (Flash)
Configuration Mode — Passive Serial (PS) / JTAG ISP
最大时钟频率 — 10 MHz
Supply Voltage - VCCINT — 3.0 V to 3.6 V / 4.75 V to 5.25 V (dual supply)
接口 — Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE)
JTAG Compliance — IEEE 1149.1 (boundary-scan, ISP)
引脚数量 — 32
Sector Architecture — Flash with built-in CRC
Cascade Support — Yes (multi-device daisy-chain)
CONF_DONE / nSTATUS Drive — Open-drain

数据手册与资源

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