EPF10K250EFC672-3 vs EPF10K250EFC672-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K250EFC672-3 sa pamamagitan ng Intel at EPF10K250EFC672-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K250EFC672-3 | EPF10K250EFC672-2 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Product Type | FPGA (Field Programmable Gate Array) | — |
| Family | FLEX 10KE | FLEX 10KE |
| Maximum Typical Gates | 250,000 | — |
| Logic Elements (LEs) | 12,160 | — |
| Embedded Memory (EAB) | 655,360 bits (80 EABs x 2,048 bits each) | — |
| Logic Array Blocks (LABs) | 392 (8 LEs per LAB) | — |
| User I/O Pins | 470 | — |
| Core Supply Voltage | 2.5 V | 2.3 V (typical 2.5 V) |
| I/O Supply Voltage | MultiVolt: 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Speed Grade | -3 (fastest) | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Packhaging | 672-ball FineLine BGA (FC) | 672-BGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch |
| Ball Pitch | 1.0 mm | — |
| Configuration Mode | JTAG (IEEE 1149.1) ISP / serial / parallel, external EPCx PROM | — |
| Process Technology | 0.25 um CMOS, 5-layer metal | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - 672-FBGA part is non-RoHS per Fly-Wing listing] | Non-RoHS Compliant (per Fly-Wing listing) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | — | 12,480 |
| Typical Gates | — | 250,000 |
| Embedded Array Blocks (EABs) | — | 20 |
| Maximum User RAM Bits | — | 40,960 |
| User I/Os | — | 470 |
| Bilang ng Pin | — | 672 |
| Propagation Delay | — | 0.4 ns |
| Temperature na Operasyon | — | 0 C to +70 C (Commercial) |
| I/O Standard Support | — | 1.8 V, 2.5 V, 3.3 V (multi-volt I/O) |
| Logic Family | — | CMOS, SRAM-based |
| Configuration | — | SRAM, in-system programmable (ISP) via JTAG |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |