EPM5016DC-20 vs EPM5032DI-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5016DC-20 sa pamamagitan ng Altera at EPM5032DI-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5016DC-20 EPM5032DI-25
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 5000 MAX 5000
Device Type EPLD (UV-Erasable Programmable Logic Device) UV-erasable Programmable Logic Device (PLD)
Macrocells 16 32
Product Terms 160 320
Dedicated Inputs 7 7
I/O Pins 8 —
Propagation Delay (tPD) 20 ns 25 ns
Maksimum na Taktiko ng Oras 62.5 MHz —
Maximum Supply Voltage 5.25 V —
Nominal Supply Voltage 5.0 V —
Process Technology CMOS, UV-erasable CMOS
Architecture PAL-type macrocell with Programmable Interconnect Array (PIA) PAL-type, CMOS, AND-OR sum-of-products
Package Type 20-pin Ceramic DIP (Cerdip) with UV window —
Package Suffix Code DC = Ceramic DIP, Commercial —
Speed Grade -20 = 20 ns tPD —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Programming Method UV erase + EPROM-style programming via Altera programming hardware —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: likely non-compliant due to ceramic DIP]
Logic Gates — [DATA_NEEDED: equivalent gate count]
Bidirectional I/O Pins — 16
Total Array Inputs — 24
Registered Outputs — 16
Global Clocks — 1
Maximum Clock Frequency (fMAX) — 62.5 MHz
Volte ng Pagbibigay — 5 V
Packhaging — Ceramic DIP, windowed (UV-erasable)
Bilang ng Pin — [DATA_NEEDED: exact pin count - 24 or 28]
I/O Standard — TTL-compatible
Programmability — UV-erasable, EPROM-based
Development Tool — MAX+PLUS II / A+PLUS
Lifecycle — Not Recommended for New Designs (NRND)

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