EPM5192AJC-25 vs EPM5192AJC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AJC-25 sa pamamagitan ng Altera at EPM5192AJC-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192AJC-25 | EPM5192AJC-15 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 5000 EPLD | MAX 5000 |
| Manufacturer | Altera (now Intel PSG) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 25 ns | — |
| Packhaging | PLCC-68 (windowed ceramic, AJC) | 84-pin PLCC (J-lead, ceramic, non-windowed) |
| Bilang ng Pin | 68 | 84 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Volte ng Pagbibigay | 5 V (typical) | — |
| Logic Blocks | MAX 5000 LABs (Logic Array Blocks) | — |
| Programmable Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Temperature na Operasyon | [DATA_NEEDED: exact operating temperature range] | 0C to +70C (commercial) |
| Erasure Method | UV-erasable (windowed ceramic package) | — |
| Programming Technology | EPROM (non-volatile) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Military Grade | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Capacity | — | 100% connectivity, sum-of-products PLA architecture |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Programmability | — | UV-erasable (windowed variant) / One-Time-Programmable |
| Toolchain | — | MAX+PLUS II |
| User I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Speed Grades Available | — | -15, -20, -25 (this part: -15) |
| Configuration Memory | — | EPROM (UV-erasable) |