EPM5192JC2 vs EPM5192JC1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC2 sa pamamagitan ng Intel at EPM5192JC1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC2 EPM5192JC1
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000 (MAX 5xxx CPLD)
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 192 —
Logic Array Blocks (LABs) 12 —
Usable Gates (equivalent) 6000 —
Maximum User I/O 64 —
Dedicated Inputs 7 —
External Clock Inputs 1 (with shared input/clock capability) —
Maksimum na Taktiko ng Oras 50 MHz —
Propagation Delay (tPD) 45 ns (speed grade -2) —
Process Technology CMOS, UV-erasable 0.5 µm CMOS, UV-erasable EPROM
Interconnect Programmable Interconnect Array (PIA) —
Packhaging PLCC-68 (JC) [DATA_NEEDED: exact package from datasheet]
Uri ng Pagpapasok Surface Mount (socketable PLCC) [DATA_NEEDED: surface mount or through-hole]
Programming Altera Master Programmer / ByteBlaster via JTAG-style interface —
Manufacturer — Intel (formerly Altera Corporation)
Macro Cells — 192
Usable Gates — 3750
Maximum Operating Frequency — 62.5 MHz
Supply Voltage (VCC) — 5 V (nominal)
Propagation Delay (typ) — [DATA_NEEDED: propagation delay in ns]
I/O Pins — [DATA_NEEDED: I/O pin count]
Temperature na Operasyon — [DATA_NEEDED: operating temp range]
Programming Interface — JTAG-compatible (Altera MAX 5xxx)
Logic Blocks (LABs) — 24 (8 macrocells per LAB)
Tindminan RoHS — unknown
AEC-Q100 — not_applicable
Lifecycle — Obsolete - last-time-buy stock only at franchised distributors

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