H5AN4G8NBJR-RDC vs MT40A512M8RH-083E Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng H5AN4G8NBJR-RDC sa pamamagitan ng SK hynix at MT40A512M8RH-083E sa pamamagitan ng Micron Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Micron Technology
MT40A512M8RH-083E - 4Gb DDR4 512Mx8 2400MHz | Micron
MT40A512M8RH-083E ✓ NakahandaPagsanggunian na paghahambing
| Parametro | H5AN4G8NBJR-RDC | MT40A512M8RH-083E |
|---|---|---|
| Brand | SK hynix | Micron Technology |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Uri ng Memory | DDR4 SDRAM | DDR4 SDRAM |
| Density | 4 Gbit | 4 Gbit |
| Organisasyon | 512M x 8 | 512M x 8 |
| Interface | DDR4 (Double Data Rate IV) | — |
| Packhaging | 78-ball FBGA | 78-ball FBGA (9 x 10.5 mm) |
| Uri ng Pagpapasok | Surface Mount | — |
| Volte ng Pagbibigay | [DATA_NEEDED: VDD supply voltage] | — |
| Rate ng Data | [DATA_NEEDED: speed grade Mbps] | — |
| Bank Architecture | 8 banks with 4 bank groups (x8) | — |
| Refresh | Auto-refresh and self-refresh | 64 ms, 8192-cycle refresh (to 95C) |
| Temperature Grade | [DATA_NEEDED: operating temperature range] | — |
| Termination | On-Die Termination (ODT) | — |
| Tindminan RoHS | Lead-Free & Halogen-Free (RoHS Compliant) | Compliant |
| Process Technology | CMOS | — |
| Manufacturer | SK hynix | — |
| Family Series | H5AN4G4/8/6NBJR | — |
| Industry Speed Grade | — | DDR4-2400 |
| Clock Rate | — | 1.2 GHz |
| Internal Banks | — | 8 banks (2 groups of 4) |
| Prefetch | — | 8n-bit |
| VDD / VDDQ | — | 1.2 V +/-60 mV |
| VPP | — | 2.5 V, -125 mV/+250 mV |
| I/O Structure | — | 1.2 V pseudo open-drain |
| VREFDQ | — | On-die internal, adjustable generation |
| Temperature na Operasyon | — | 0C to +95C |
| FBGA Code | — | D9TGG |
| Marking Code | — | D9TGG |
| Data Strobe Preamble | — | Programmable |
| Latensya ng CAS | — | [DATA_NEEDED: CAS latency per speed bin table] |