H5AN8G6NDJR vs H5AN8G6NAFR-UHC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng H5AN8G6NDJR sa pamamagitan ng SK hynix at H5AN8G6NAFR-UHC sa pamamagitan ng SK hynix. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | H5AN8G6NDJR | H5AN8G6NAFR-UHC |
|---|---|---|
| Brand | SK hynix | SK hynix |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Uri ng Memory | DDR4 SDRAM | DDR4 SDRAM (CMOS) |
| Density | 8 Gb | — |
| Organisasyon | 512M x 16 | 512M x 16 |
| Rate ng Data | 3200 Mbps (DDR4-3200) | 2400 MT/s |
| Volte ng Pagbibigay | 1.2 V | 1.2 V |
| Packhaging | 96-ball FBGA (13mm x 7.5mm) | 96-ball FBGA (TFBGA) |
| Number of Terminals | 96 | — |
| Maximum Supply Voltage (Vsup) | 1.26 V | — |
| Maximum Operating Temperature | 85 °C | — |
| Burst Length | 8 (BL8), 4 (BC4) | — |
| Latensya ng CAS | 22 cycles (at 3200 Mbps) | — |
| Access Mode | Multi Bank Page Burst | — |
| JESD-30 Code | R-PBGA-B96 | — |
| RoHS | Compliant | — |
| Mga Karakteristika | Auto self-refresh, auto precharge, asynchronous reset, data mask, dynamic ODT, ZQ calibration, CRC, write leveling | — |
| Memory Density | — | 8 Gbit |
| Clock Architecture | — | Differential clock (CK_t / CK_c), fully synchronous |
| Uri ng Pagpapasok | — | Surface Mount |
| Temperature na Operasyon | — | 0C to +85C |
| Refresh | — | Auto self-refresh |
| Precharge | — | Auto precharge function |
| Reset | — | Asynchronous reset function |
| Data Mask | — | DM function supported |
| Termination | — | Dynamic on-chip termination (ODT) |
| Calibration | — | ZQ calibration function |
| Error Checking | — | CRC function |
| Write Leveling | — | Write leveling function supported |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |