H5AN8G6NDJR vs H5AN8G6NAFR-UHC 比較
詳細並排比較 H5AN8G6NDJR 由 SK hynix 與 H5AN8G6NAFR-UHC 由 SK hynix. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | H5AN8G6NDJR | H5AN8G6NAFR-UHC |
|---|---|---|
| 品牌 | SK hynix | SK hynix |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 記憶體類型 | DDR4 SDRAM | DDR4 SDRAM (CMOS) |
| Density | 8 Gb | — |
| 組織 | 512M x 16 | 512M x 16 |
| 資料速率 | 3200 Mbps (DDR4-3200) | 2400 MT/s |
| 供應電壓 | 1.2 V | 1.2 V |
| 封裝 | 96-ball FBGA (13mm x 7.5mm) | 96-ball FBGA (TFBGA) |
| Number of Terminals | 96 | — |
| Maximum Supply Voltage (Vsup) | 1.26 V | — |
| Maximum Operating Temperature | 85 °C | — |
| Burst Length | 8 (BL8), 4 (BC4) | — |
| CAS 延遲 | 22 cycles (at 3200 Mbps) | — |
| Access Mode | Multi Bank Page Burst | — |
| JESD-30 Code | R-PBGA-B96 | — |
| RoHS | Compliant | — |
| 功能特色 | Auto self-refresh, auto precharge, asynchronous reset, data mask, dynamic ODT, ZQ calibration, CRC, write leveling | — |
| Memory Density | — | 8 Gbit |
| Clock Architecture | — | Differential clock (CK_t / CK_c), fully synchronous |
| 安裝類型 | — | Surface Mount |
| 工作溫度 | — | 0C to +85C |
| Refresh | — | Auto self-refresh |
| Precharge | — | Auto precharge function |
| Reset | — | Asynchronous reset function |
| Data Mask | — | DM function supported |
| Termination | — | Dynamic on-chip termination (ODT) |
| Calibration | — | ZQ calibration function |
| Error Checking | — | CRC function |
| Write Leveling | — | Write leveling function supported |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |