ADC/DAC
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LTC2165IUK - 16-Bit 125Msps Low Power ADC | Analog Devices
The Analog Devices LTC2165IUK is a 16-bit, 125 Msps low-power pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7 mm) UK package. It supports one differential or single-ended analog input and delivers 76.8 dB SNR with 90 dB spurious-free dynamic range, making it well-suited for digitizing high-frequency wideband signals in communications and instrumentation applications. An ADC, or analog-to-digital converter, is a semiconductor device that samples continuous analog voltage signals and converts them into discrete digital codes at a specified sampling rate. Pipelined ADCs like the LTC2165 employ a multi-stage sub-ADC architecture that interleaves conversions to achieve high sample rates while maintaining low power and small die area. They sit within the broader hierarchy of data converters, which includes successive-approximation (SAR), delta-sigma, and flash ADCs, and are the workhorse of high-speed signal acquisition systems. Key features of the LTC2165IUK include ultralow 0.07 ps RMS aperture jitter for accurate undersampling of IF frequencies, selectable LVDS/CMOS output modes for flexible board interfacing, an internal 2.5 V reference, and a maximum power dissipation of 314 mW at full 125 Msps operation. The pipelined architecture introduces a fixed conversion latency but supports continuous streaming with no cycle loss in either the CMOS or LVDS mode. The LTC2165IUK shares an identical pinout with the lower-speed LTC2164 (105 Msps) and LTC2163 (80 Msps) variants, allowing a single PCB layout to serve multiple performance targets. Digital outputs can be configured as full-rate CMOS, multiplexed CMOS for low-pin-count interfaces, or LVDS for high-noise-immunity backplanes. An internal reference and flexible input common-mode range simplify the analog front-end design. Typical applications include multiband, multimode cellular base-station receivers, software-defined radio (SDR) front ends, low-power handheld test instruments, medical imaging receivers, and spectrum analysis systems. The 125 Msps sampling rate combined with 16-bit resolution allows direct digitization of signals at IF frequencies such as 70 MHz or 140 MHz, simplifying receiver signal chains. Designers should pay attention to analog input network design: a wideband transformer or differential amplifier driver is recommended to preserve SFDR at high input frequencies, and a low-jitter sampling clock must be provided through a CMOS or LVPECL source to maintain the rated SNR. Decoupling must include a low-inductance 1 uF and 0.1 uF pair near the supply pins. This page synthesizes distributor pricing, pin-compatible speed-grade alternatives within the LTC2163/2164/2165 family, and practical design notes not found concisely in the manufacturer datasheet.
LTC2170CUKG-12 - 12-Bit Quad 25Msps ADC | Analog Devices
The Analog Devices LTC2170CUKG-12 is a 12-bit, 4-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) supporting up to 25 Msps per channel, packaged in a 52-pin QFN (7 mm x 8 mm). It is pin-compatible with the 14-bit LTC2170-14 family members, enabling a single PCB design to be populated with 12-bit or 14-bit resolution parts without layout changes. The part operates from a single 1.8 V supply, dissipating approximately 160 mW total (40 mW per channel), making it one of the lowest-power quad 12-bit ADCs in its speed class. What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage converter architecture that processes one sample per clock cycle after an initial pipeline-fill latency, providing an excellent trade-off between speed, resolution, and power consumption. Pipelined ADCs sit in the hierarchy of ADC architectures between flash converters (highest speed, lowest resolution) and successive-approximation-register (SAR) converters (lowest speed, highest accuracy at low sample rates), and are widely used in communications, imaging, and multi-channel data acquisition where tens of Msps are required with moderate resolution. Key features of the LTC2170CUKG-12 include 4 simultaneous-sampling differential or single-ended inputs, 800 MHz full-power analog input bandwidth, selectable input ranges of 1 Vp-p to 2 Vp-p, a sample-and-hold on each channel, 90 dB spurious-free dynamic range (SFDR), serial LVDS digital outputs (one or two bits per channel), and an SPI port for configuration. Shutdown and Nap modes reduce power during idle periods for battery-sensitive applications. The device uses a 1.8 V analog supply plus an optional 1.8 V digital supply, with an internal PLL generating all required clock phases. Its 52-pin QFN package provides a compact footprint and an exposed pad for thermal management, supporting reliable operation across the -40 °C to +85 °C commercial temperature range. Typical applications include multi-channel digital oscilloscopes, phased-array ultrasound receivers, MIMO wireless infrastructure baseband digitizers, radar and electronic-warfare front ends, medical imaging receivers, and high-speed data acquisition cards for industrial test equipment. The 4-channel simultaneous sampling is particularly valuable when channel-to-channel phase relationships must be preserved. When designing with this part, ensure the analog input is AC- or DC-coupled through a wideband low-distortion driver, place 0.1 µF bypass capacitors as close as possible to every supply pin, and provide a 100 Ω differential termination at each LVDS output pair. Verify the encoder/decoder mode and serial LVDS data-rate configuration through the SPI port during board bring-up. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and qualifying the LTC2170CUKG-12.
LTC2170CUKG-14 - 14-Bit, 25Msps Low Power Quad ADC | ADI
The Analog Devices LTC2170CUKG-14 is a 14-bit, 25Msps low-power quad analog-to-digital converter (ADC) housed in a 52-pin QFN (7 mm x 8 mm) package with exposed thermal pad. It integrates four simultaneously-sampling pipelined ADC channels with 90 dB SFDR, sample-and-hold front-ends, and selectable serial LVDS outputs (one or two bits per channel), making it ideal for multi-channel baseband digitisation where PCB real estate is constrained. A pipelined ADC is a high-speed converter architecture that resolves an analog input through a cascade of low-resolution stages with inter-stage digital error correction. Quad-channel ADCs like the LTC2170-14 family fall under the broader data-converter hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. By sharing one clock, reference and digital interface across four channels, designers replace four discrete ADC ICs, reducing BOM count, board area, and channel-to-channel skew compared to discrete multi-ADC solutions. Key specifications include 14-bit resolution at 25 Msps per channel, 90 dB spurious-free dynamic range (SFDR), single 1.8 V supply operation, and total power dissipation of 162 mW (about 41 mW per channel). Each channel has 800 MHz full-power analogue bandwidth, selectable 1 Vp-p or 2 Vp-p input ranges, an integrated sample-and-hold, plus shutdown and nap modes controlled through the serial SPI configuration port. The 52-pin QFN package offers low thermal resistance via the bottom exposed pad for heat transfer into the PCB copper plane. Typical applications include portable ultrasound imaging, multi-channel communication receivers, low-power instrumentation, and industrial imaging arrays. The pin-compatible 12-bit and 14-bit family members (LTC2170-12 / LTC2170-14) share the same footprint, allowing system designers to upgrade resolution or sample rate by simply substituting parts on an existing layout.
LTC2170IUKG-12 - 12-Bit 25Msps Quad ADC | Analog Devices
The Analog Devices LTC2170IUKG-12 is a 4-channel, simultaneous-sampling 12-bit analog-to-digital converter (ADC) operating at 25 Msps per channel, housed in a 52-pin QFN (7 mm x 8 mm) package. The part is built on a pipelined architecture and is part of the pin-compatible LTC2172/LTC2171/LTC2170 family, which offers 65 Msps, 40 Msps, and 25 Msps speed grades, allowing designers to scale sampling rate without changing the PCB layout. What is a quad ADC? A quad ADC is an integrated circuit that contains four matched ADC cores and a shared reference, clock, and digital interface. By integrating four converters into one package, the quad ADC removes channel-to-channel timing skew and simplifies PCB routing for multi-channel data acquisition systems. A pipelined ADC converts an analog input by passing the sampled voltage through a cascade of low-resolution stages, producing a high throughput at moderate resolution. Quad ADCs sit inside the hierarchy of data-converter ICs -> ADC -> high-speed ADC -> pipelined ADC -> simultaneous-sampling ADC -> semiconductor. Key features of the LTC2170-12 include 71 dB SNR and 90 dB spurious-free dynamic range (SFDR), 0.15 ps RMS aperture jitter for accurate undersampling of IF signals, and an 800 MHz full-power input bandwidth. The serial LVDS digital interface supports both 1-lane (one bit per channel per cycle) and 2-lane (two bits per channel per cycle) modes, minimizing the number of board traces between the ADC and the FPGA/ASIC. A serial SPI port configures output mode, input range, and channel shutdown. Selectable input ranges of 1 Vp-p to 2 Vp-p enable direct connection to most IF and baseband drivers without external attenuators. Typical applications include multi-channel communications receivers, phased-array antenna digitizers, medical imaging front ends, and industrial ultrasound beamformers. The wide input bandwidth and low jitter also make the part well suited to undersampling of intermediate-frequency signals in software-defined radio (SDR) platforms. When designing with this part, follow the recommended layout in the manufacturer datasheet: keep analog input traces length-matched and surrounded by a continuous ground plane, place the 1.8 V supply decoupling within 5 mm of the ADJ pin, and route the LVDS pairs as 100 ohm differential lines to the FPGA. The exposed pad (EP) on the bottom of the QFN must be soldered to a ground pad for thermal and electrical performance.
LTC2170IUKG-14 - 14-Bit 25Msps Quad ADC | Analog Devices
The Analog Devices LTC2170IUKG-14 is a 14-bit, 25 Msps, low-power quad analog-to-digital converter (ADC) housed in a 52-lead QFN (7x8 mm) package with an exposed pad for thermal dissipation. The device integrates four simultaneously-sampling pipelined ADC channels, supports a 1.7 V to 1.9 V analog/digital supply, and provides selectable parallel CMOS or serialized LVDS outputs for flexible downstream interface. A pipelined ADC is a high-speed successive-approximation architecture that breaks the conversion into multiple low-resolution stages, each driving the next through a residue amplifier. This architecture enables simultaneous multi-channel sampling at tens of megasamples per second while keeping per-channel power modest, which is why quad pipelined ADCs dominate communications, radar, and medical imaging front-ends where dense channel counts matter. The LTC2170 sits within the broader product taxonomy as: pipelined ADC -> successive-approximation/flash-pipelined ADC -> analog-to-digital converter -> data converter -> mixed-signal IC -> semiconductor. Key features include per-channel sample rates up to 25 Msps, 14-bit resolution, four independent differential or single-ended analog inputs, integrated input buffer option, programmable full-scale range via internal reference, pin-selectable CMOS or LVDS output modes, and a per-channel SNR figure consistent with the family datasheet. The exposed pad on the QFN package transfers die heat directly into the PCB copper pour, reducing junction temperature and enabling sustained full-rate operation across all four channels. Typical applications include diversity radio receivers, multi-antenna MIMO baseband digitizers, portable or battery-powered test and measurement instruments, ultrasound imaging front-ends, and any system that requires dense multi-channel simultaneous sampling without the cost of four discrete ADCs. The serial LVDS mode minimizes board routing for high-density systems, while parallel CMOS remains useful for legacy FPGA or ASIC capture. When laying out the PCB, ensure the exposed pad is soldered to a continuous ground plane with multiple thermal vias to dissipate roughly 1 W of total device dissipation. Decouple OVD and AVD rails independently with 0.1 uF and 10 uF ceramic capacitors placed as close as possible to the supply pins, and keep analog inputs routed over a contiguous ground reference.
LTC2171CUKG-12 - 12-Bit 40Msps Quad ADC, 1.8V, 52-QFN | ADI
The Analog Devices LTC2171CUKG-12 is a 12-bit, 40 Msps, low-power, 4-channel analog-to-digital converter (ADC) housed in a 52-lead QFN (7mm x 8mm) package with an exposed pad, powered by a single 1.8 V supply and featuring serial LVDS digital outputs. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous-time analog waveforms into discrete digital codes at a specified sample rate. The LTC2171 family belongs to the pipelined ADC category, sitting in the hierarchy: pipelined ADC -> Nyquist ADC -> data converter -> mixed-signal IC -> semiconductor. Pipelined architectures achieve high sample rates (>10 Msps) while maintaining 10- to 14-bit resolution, making them dominant in communications, imaging, and multi-channel data acquisition. Key features of this device include ±0.3 LSB typical INL (Integral Non-Linearity), ±0.1 LSB typical DNL (Differential Non-Linearity), no missing codes over the full operating temperature range, and an exceptionally low 0.3 LSB RMS transition noise. The differential analog inputs must be driven differentially to achieve full performance, and the LVDS outputs minimize data-line count via configurable 1-lane or 2-lane modes, each carrying either 1 or 2 bits per channel per clock cycle. Technical depth: the pipelined architecture uses multiple low-resolution stages with residue amplification, allowing the chip to digitize at 40 Msps while consuming minimal power per channel. Each ADC input integrates a wideband track-and-hold and a precision reference buffer, supporting single-ended or differential drive topologies. The 4 channels are sampled simultaneously, which is essential for phased-array antenna systems and quad-receiver I/Q baseband chains. Typical applications include multi-channel digital oscilloscopes, communications baseband receivers, medical imaging systems, and 4-channel simultaneous-sampling data acquisition cards. The combination of 4 synchronized channels and LVDS digital outputs makes it ideal for systems where PCB trace routing density is constrained. A key design consideration is that the analog inputs require differential drive for full 12-bit dynamic range; a single-ended input will degrade SNR and linearity. The exposed pad must be soldered to a low-impedance ground plane for thermal dissipation and to provide the ground reference for the differential inputs. This page synthesizes distributor pricing, same-family drop-in cross references, and practical multi-channel PCB layout guidance not found in the manufacturer datasheet alone.
LTC2171CUKG-14 - 14-Bit 40Msps Quad ADC | Analog Devices
The Analog Devices LTC2171CUKG-14 is a 14-bit, 40 Msps, low-power quad-channel pipelined analog-to-digital converter (ADC) housed in a 52-pin QFN (7 mm × 8 mm) package with an exposed thermal pad. Each of the four simultaneously-sampling channels delivers 14-bit resolution at up to 40 Msps, drawing approximately 78 mW per channel (311 mW total) from a single 1.8 V supply, making the device a strong fit for multi-channel low-power imaging and communications designs. An ADC (analog-to-digital converter) is a semiconductor device that samples a continuous-time analog signal and converts each sample into a discrete digital code. Pipelined ADCs use a multi-stage architecture in which each stage performs a low-resolution conversion and passes the residue to the next stage, enabling high sampling rates with low power consumption. Quad (4-channel) ADCs like the LTC2171CUKG-14 belong to the family of simultaneous-sampling data converters used in systems that require multiple analog inputs to be captured at the same instant, such as phased-array receivers, multi-antenna base stations, and medical imaging front-ends. The LTC2171CUKG-14 features ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over temperature, and 1.2 LSB RMS transition noise. SFDR is 90 dB, and the device achieves an 800 MHz full-power analog input bandwidth. The digital interface is serial LVDS, configurable as one bit per channel (1-lane mode) or two bits per channel (2-lane mode), reducing pin count and easing FPGA/CPLD interconnect. Selectable input ranges of 1 Vp-p to 2 Vp-p allow direct connection to a wide range of front-end amplifiers and IF stages. The device includes shutdown and nap power-saving modes, a sample-and-hold amplifier on every channel, and a serial SPI port for mode configuration. The 52-pin QFN package uses a bottom-side exposed pad that conducts the majority of die heat into the PCB, requiring careful thermal layout (multiple thermal vias under the EP) for reliable operation. Pin-compatible 14-bit and 12-bit versions exist within the LTC2170/LTC2171/LTC2150/LTC2151 family, allowing resolution scaling without PCB redesign. Typical applications include multi-carrier cellular base-station receivers, portable ultrasound imaging, non-invasive medical instrumentation, multi-antenna diversity receivers, and industrial multichannel data acquisition. The combination of quad simultaneous sampling, low power, and serial LVDS outputs also suits phased-array radar, software-defined radio (SDR), and handheld test equipment. A key design consideration is that the LVDS interface requires a 100 Ω termination at the receiver and matched-length PCB traces; the analog inputs are differential and should be AC- or DC-coupled through a balun or driver such as the ADA4927 for best second-order distortion performance. Decoupling the 1.8 V analog and digital supplies separately near the EP ground is essential to keep digital switching noise out of the analog front end. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not all available in a single manufacturer datasheet, with cross-references to same-family and same-package parts (LTC2170, LTC2151, LTC2150, LTC2145) for design flexibility.
LTC2171IUKG-12 - 12-Bit 40Msps Quad ADC, 1.8V Serial LVDS | ADI
The Analog Devices LTC2171IUKG-12 is a 12-bit, 40Msps, low-power, 4-channel pipelined analog-to-digital converter (ADC) housed in a 52-pin (7mm x 8mm) QFN package. It is powered from a single 1.8V supply, integrates four simultaneously-sampling channels, and serializes data output as serial LVDS to minimize the number of data lines routed on the PCB, with selectable 2-lane or 1-lane output mode per channel. Differential analog inputs drive an internal sample-and-hold with 800MHz full-power bandwidth, allowing the converter to handle IF sampling well beyond Nyquist. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed successive-approximation architecture optimized for sample rates from a few MS/s to over 100 MS/s, where multiple low-resolution stages resolve each conversion in parallel. Pipelined ADCs are the workhorse of communications, instrumentation, and multichannel data-acquisition designs because they achieve excellent dynamic range at moderate power budgets and are easily replicated for simultaneous multi-channel acquisition. In the broader product taxonomy, the LTC2171IUKG-12 is an ADC -> data converter -> signal chain IC -> semiconductor device. Key specifications include +/-0.3 LSB INL (typical) and +/-0.1 LSB DNL (typical) with no missing codes over the full temperature range, transition noise of 0.3 LSB RMS, and integrated shutdown and nap modes controlled through a serial SPI port. The 52-pin QFN-52 (UKG) 7mm x 8mm package is pin-compatible with 14-bit and 12-bit speed grades in the LTC2170/2171/2172 family, giving designers a clear upgrade path across resolution and sample-rate combinations. The serial LVDS interface reduces FPGA pin count and PCB routing complexity compared with parallel CMOS outputs, allowing longer trace lengths without compromising timing. Pairing with a low-jitter differential clock and an Analog Devices ADA4927 driver typically achieves optimum SFDR at intermediate frequencies used in wireless baseband, ultrasound beamformers, and portable test instrumentation. Typical applications include medical ultrasound imaging, communications infrastructure receivers, multichannel data acquisition, and portable battery-powered test equipment. The device is also widely deployed in digital oscilloscopes and spectrum analyzers where density of analog front-end channels and low per-channel power are critical. When designing with this device, route LVDS pairs as 100 ohm differential lines with matched length, place the analog input RC network as close to the AI pins as possible, and provide a low-noise 1.8V rail with adequate decoupling to preserve SFDR. The shutdown and nap modes should be used in battery-powered designs to reduce quiescent draw when the converter is idle. This page aggregates distributor pricing, drop-in alternatives, and practical design notes for the LTC2171IUKG-12 that complement the official Analog Devices datasheet for faster component evaluation.
LTC2172CUKG-12 - 12-Bit 65Msps Quad ADC LVDS | Analog Devices
The Analog Devices LTC2172CUKG-12 is a 12-bit, 65 Msps, low-power quad analog-to-digital converter (ADC) housed in a 52-pin QFN (7 mm × 8 mm) package. It features four simultaneously-sampling pipelined ADC channels, a 1.8 V single supply rail, and 1 V P-P to 2 V P-P selectable input ranges. According to the LTC2172-12 datasheet, the part is pin-compatible with 14-bit and 12-bit family members (LTC2172-14, LTC2171-12, LTC2170-12). An ADC (analog-to-digital converter) is a semiconductor that converts continuous analog waveforms into discrete digital codes at a specified sample rate. Quad ADCs such as the LTC2172CUKG-12 integrate four independent conversion channels on a single die, allowing simultaneous sampling of multiple signals - useful in MIMO transceivers, multi-antenna base stations, medical imaging arrays, and beamforming systems. Low-power quad ADCs sit at the intersection of high-speed data conversion and energy-efficient system design, supporting both battery-powered portable instruments and dense multi-channel rack equipment. Key specifications for the LTC2172CUKG-12 include 65 Msps sampling rate, 12-bit resolution, LVDS digital outputs with 3.5 mA drive and 1.25 V common-mode voltage, 1.8 V single-supply operation, 800 MHz full-power analog input bandwidth, integrated sample-and-hold, configurable shutdown and nap modes, and an SPI configuration port for register control. The selectable input range (1 V P-P or 2 V P-P) enables direct interfacing to a wide range of IF/RF signal chains without external attenuators. Architecturally, the LTC2172CUKG-12 uses a pipelined multi-stage ADC core per channel, which provides an excellent speed-resolution trade-off: each stage resolves a few bits and passes the residue to the next, allowing very high clock rates while keeping per-stage capacitor area modest. Differential analog inputs with on-chip common-mode bias simplify transformer or op-amp driver interfacing. Typical applications include 4G LTE and diversity radio receiver basebands, multi-channel communications test equipment, handheld and portable imaging systems, medical ultrasound front-ends, and multi-antenna phased-array radar digitizers. Its low power draw makes it suitable for thermally constrained enclosures. When designing with this device, AC-couple or DC-couple the analog inputs through a differential driver, place the LVDS 100 Ω termination resistors as close as possible to the FPGA/ASIC LVDS pins, and use a low-noise LDO (such as the ADP1740) to derive the 1.8 V analog supply from a switching pre-regulator. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design guidance not found in the manufacturer datasheet alone.
LTC2172IUKG-12 - 12-Bit 65Msps Quad ADC, 52-QFN | Analog Devices
The Analog Devices LTC2172IUKG-12 is a 12-bit, 65 Msps, low-power quad simultaneous-sampling analog-to-digital converter (ADC) housed in a 52-pin 7 mm x 8 mm QFN package. It provides four 12-bit pipelined ADC channels sampling at up to 65 Msps per channel, designed for digitizing high-frequency, wide-dynamic-range signals. The LTC2172-12 family (LTC2170-12, LTC2171-12, LTC2172-12) is pin-compatible with the 14-bit LTC2170-14/2171-14/2172-14 family, allowing system designers to migrate resolution without PCB rework. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes. The pipelined ADC architecture used in the LTC2172-12 family combines multiple low-resolution flash stages to achieve high sampling rates with low power consumption. The simultaneous-sampling quad-channel configuration is essential in applications where phase and amplitude relationships between channels must be preserved, such as in multi-antenna receivers, phased-array beamformers, and multi-channel test instrumentation. Key features of the LTC2172IUKG-12 include 800 MHz full-power input bandwidth, individual channel shutdown and nap modes for power savings, a serial SPI port for configuration, and pin-compatibility with the 14-bit version. The device accepts differential inputs and outputs data in LVDS or CMOS formats, supporting flexible interface integration with FPGAs and DSPs. Typical SNR of approximately 70 dBFS at 65 Msps makes it suitable for communication infrastructure and industrial imaging systems. Typical applications include communications receivers, cellular base-station digitizers, multi-channel data acquisition systems, medical imaging front ends, and portable or battery-powered instrumentation. The simultaneous-sampling nature preserves time-domain coherence across all four channels, which is critical for phased-array radar, ultrasound beamforming, and MIMO wireless front ends where mismatched sampling times would corrupt beam-steering calculations. When designing with this part, place the analog input traces in a symmetric layout and route LVDS output pairs with controlled 100 ohm differential impedance. Use solid ground planes under the QFN thermal pad and stitch vias to inner ground layers to maintain low digital-to-analog crosstalk and ensure the 800 MHz input bandwidth is realized in practice.
LTC2173IUKG-14 - 14-Bit 80Msps Quad ADC | Analog Devices
The Analog Devices LTC2173IUKG-14 is a 14-bit, 80 Msps, low-power quad analog-to-digital converter (ADC) housed in a 52-pin QFN (7x8 mm) package. It integrates four simultaneously-sampling pipelined ADC channels with serialized LVDS outputs, designed for digitizing high-frequency, wide-dynamic-range signals in compact form factors. Each channel consumes approximately 120 mW at 80 Msps, and the device supports selectable digital gain and a flexible LVDS serial output interface. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes. Quad ADCs integrate four converter channels on a single die, enabling simultaneous sampling of multiple signals - critical for multi-channel communication, phased-array radar, and medical imaging systems. The LTC2173IUKG-14 belongs to the pipelined ADC architecture family, where each conversion stage processes a few bits and passes the residue to the next stage; this allows high sample rates with low power per channel. Within the broader product taxonomy, this part falls under ADC -> data converter -> signal chain IC -> semiconductor. Key specifications include 14-bit resolution, 80 Msps sample rate per channel, 73.1 dB SNR (typical at 14 MHz input), 90 dB SFDR, and 1.4 GHz analog input bandwidth. The device operates from a single 1.8 V supply, supports LVDS/LVCMOS output formats, and offers a serial SPI port for mode programming. It also integrates an internal bandgap reference and provides per-channel offset calibration. The pipeline architecture delivers 80 Msps sample rates with only 4 clock cycles of latency, making the LTC2173IUKG-14 well-suited for real-time signal processing. Its low power consumption allows dense multi-channel layouts without complex thermal management. The 52-pin QFN package exposes the thermal die pad for direct PCB heat dissipation, simplifying board design in space-constrained applications. Typical applications include multi-carrier wireless base station receivers, portable ultrasound imaging front-ends, industrial data acquisition systems, and software-defined radio (SDR) platforms. Engineers value this part for its ability to capture four synchronized analog signals in a small footprint while maintaining excellent dynamic range. When designing with this ADC, allocate at least 4 layers for the PCB with a continuous ground plane under the QFN thermal pad. Use 0.1 uF and 10 uF decoupling capacitors close to each supply pin, and route LVDS output pairs with 100 ohm differential impedance and length matching within 5 mm to preserve SNR. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical layout notes not found in the manufacturer datasheet.
LTC2174CUKG-14 - 14-Bit 105Msps Quad ADC | Analog Devices
The Analog Devices LTC2174CUKG-14 is a 14-bit, 105 Msps, 4-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 52-pin QFN (7x8 mm) package with an exposed thermal pad. It belongs to the LTC2175-14/LTC2174-14/LTC2173-14 family and is designed for digitizing high-frequency, wide-dynamic-range signals with low power consumption and excellent AC performance. Background: A pipelined analog-to-digital converter (ADC) is a high-speed data conversion architecture that processes analog input samples through cascaded low-resolution stages, each driving a residue into the next stage. Compared to successive-approximation register (SAR) ADCs, pipelined converters deliver far higher sampling rates (tens to hundreds of Msps) at the cost of fixed pipeline latency. Multi-channel, simultaneous-sampling pipelined ADCs such as the LTC2174-14 are essential for multi-antenna or multi-phase signal chains where phase coherence between channels must be preserved - the family hierarchy is: ADC -> pipelined ADC -> simultaneous-sampling ADC -> power management IC adjacent function. Key features of the LTC2174CUKG-14 include 4 simultaneously sampling 14-bit inputs, 105 Msps per channel conversion rate, a single 1.7 V to 1.9 V supply, integrated CMOS or LVDS digital outputs, and built-in clock duty-cycle stabilization. The 52-QFN (7x8) package provides a low-thermal-resistance exposed pad, which is required for heat extraction when running all four channels at full 105 Msps clock. Technically, the converter uses a multi-stage differential pipelined architecture with proprietary digital calibration to correct capacitor mismatch and comparator offset, achieving 14-bit linearity across the rated input bandwidth. The differential sample-and-hold front end supports wideband IF sampling, while the output stage is configurable for full-rate CMOS or double-data-rate LVDS to ease FPGA interface timing. Typical applications for the LTC2174CUKG-14 include multi-channel communications receivers, broadband software-defined radio, phased-array radar and beamforming front ends, medical ultrasound imaging, and high-speed industrial data acquisition. The wide input bandwidth and simultaneous sampling make it especially suitable for diversity receivers and I/Q demodulation paths. Design consideration: For multi-channel operation at full speed, the exposed pad must be soldered to a continuous ground copper pour with thermal vias; insufficient heat-sinking will trigger thermal shutdown under continuous 105 Msps sampling. Unique value: This page synthesizes distributor pricing, drop-in pin-compatible variants (LTC2173-14 80 Msps, LTC2175-14 125 Msps), and PCB layout guidance not collected in any single manufacturer datasheet.
LTC2174IUKG-14 - 14-Bit 105Msps Quad ADC | Analog Devices
The Analog Devices LTC2174IUKG-14 is a 14-bit, 105 Msps, low-power, four-channel pipelined analog-to-digital converter housed in a 52-pin QFN (7x8 mm) package with an exposed thermal pad. Each of the four simultaneously-sampling channels achieves 73.5 dB SNR and 90 dB SFDR at the rated 105 Msps, while total typical power dissipation is held to roughly 410 mW across all four ADCs. The I-suffix variant is specified for the industrial temperature range of -40 °C to +85 °C, and the device offers LVDS and serial CMOS output formats with a 74.25 MHz DDR clock interface. Sampling-rate options of 105 Msps (LTC2174), 125 Msps (LTC2175) and 80 Msps (LTC2173) share one datasheet and pinout. A pipelined ADC is an analog-to-digital converter that processes input samples through a cascade of low-resolution flash stages and a digital correction backend, allowing high sampling rates at moderate resolution. Quad ADC ICs package four matched converter channels into one die so that multi-antenna or multi-channel receiver systems can capture synchronized samples without skew between channels. This places the LTC2174 in the broader IC hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Such parts are essential building blocks in 4G LTE base-station digitizers, multi-channel software-defined radio receivers, medical ultrasound beamformers, and any application where four coherent high-speed data streams must be captured at once. Key features of the LTC2174IUKG-14 include selectable internal 2.2 Vp-p or 1 Vp-p input ranges, an integrated clock duty-cycle stabilizer, and a programmable digital output test pattern generator that aids board-level bring-up. A low-latency LVDS mode reduces the number of output pairs per channel from five to two at higher output frequencies, simplifying board routing in dense multi-channel designs. The optional serial CMOS mode supports 14-bit offset-binary, two's-complement or Gray-coded outputs, easing interconnection to FPGAs and ASICs. Architecturally the part uses four matched pipelined cores sharing a common reference and clock tree, plus a per-channel track-and-hold. The exposed die pad provides a low thermal-resistance path (theta_JA about 25 °C/W on a standard 4-layer JEDEC test board) so the converter can deliver full performance without forced-air cooling in most embedded designs. Power can be scaled down by clock gating unused channels via the serial configuration port. Typical applications include cellular base-station receivers, multi-channel IF-sampling SDR cards, portable ultrasound front-ends, and multi-antenna spectrum-analysis acquisition boards. The combination of four matched channels, 14-bit resolution, and a low 410 mW typical power makes the part suitable for fan-out-limited enclosures. Designers should respect the 7x8 mm QFN land pattern and provide sufficient copper area beneath the exposed pad to keep junction temperatures within the industrial range, as well as follow the standard analog supply decoupling topology from the datasheet.
LTC2175CUKG-14 - 14-Bit 125Msps Quad ADC | Analog Devices
The Analog Devices LTC2175CUKG-14 is a 14-bit, 125 Msps low-power quad analog-to-digital converter (ADC) housed in a 52-pin QFN (7mm x 8mm) package with an exposed pad for thermal dissipation. It integrates four simultaneously-sampling pipelined ADC channels, each delivering 14-bit resolution at up to 125 Msps with serialized LVDS digital outputs. The LTC2175CUKG-14 is the commercial temperature grade variant of the LTC2175 family, supporting 0C to +70C operation, and is orderable in tape-and-reel with the #PBF lead-free finish. A pipelined ADC is a multi-stage converter architecture that uses successive low-resolution flash stages and digital correction to achieve high sample rates while keeping per-stage comparator count and power consumption low compared to a full-flash converter. The LTC2175 family sits in the broader taxonomy of Nyquist-rate ADCs, distinguishing from successive-approximation register (SAR) and delta-sigma ADCs by its high sampling rate and moderate per-channel latency. Within the signal chain, the quad-channel integration reduces board area for parallel-channel systems such as multi-antenna receivers or quadrature IF sampling. Key specifications include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes across the operating temperature range, and 1.2 LSB RMS transition noise. Each channel supports two LVDS output lanes by default, with a one-bit-per-channel mode configurable at lower sampling rates. The serial LVDS interface minimizes the number of board data traces, simplifying PCB routing in dense multi-channel designs. The device is optimized for low power consumption, with most thermal dissipation transferred through the bottom-side exposed pad onto the PCB copper. Designers should follow the recommended PCB layout for the exposed pad and provide adequate ground and supply decoupling around each analog input pin. The combination of four channels, 14-bit resolution, and 125 Msps sampling rate makes the LTC2175CUKG-14 well suited to communications infrastructure, multi-antenna diversity receivers, I/Q baseband sampling, and portable test instrumentation. When integrating this ADC, ensure that the analog inputs are AC- or DC-coupled through properly sized transformer or driver networks, that the sample clock has low jitter for SNR preservation, and that the LVDS output lanes are length-matched with controlled impedance. The exposed pad must be soldered to a sufficient copper pour to keep junction temperature within the derated limit at maximum sample rate and ambient. This page synthesizes distributor availability, drop-in same-family alternatives, and PCB-level design notes that go beyond the manufacturer datasheet to assist engineers evaluating the LTC2175CUKG-14 for next-generation multi-channel receiver or instrumentation designs.
LTC2175IUKG-12 - 12-Bit 125Msps Quad ADC, Serial LVDS | ADI
The Analog Devices LTC2175IUKG-12 is a 12-bit, 125 Msps, low-power, 4-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 52-pin QFN (7x8 mm) package with exposed thermal pad. Each of its four input channels incorporates an independent track-and-hold and pipeline architecture, enabling per-channel digitization up to 125 Msps. The digital outputs are serial LVDS (2-lane mode default; 1-lane mode available at lower sampling rates) to minimize data-line count on the PCB. An ADC is a mixed-signal integrated circuit that converts continuous analog waveforms into discrete digital codes; pipelined ADCs specifically use a multi-stage switched-capacitor architecture to balance high sampling speed against moderate die area and power dissipation. The LTC2175 family sits inside the converter hierarchy as: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. It therefore serves wherever simultaneous multi-channel wide-bandwidth capture is needed, including communications baseband, radar, and instrumentation front ends. Key features include ±0.3 LSB INL (typical) and ±0.1 LSB DNL (typical) with no missing codes over the full operating temperature range, plus a low 0.3 LSB RMS transition noise. The 52-pin QFN package provides a compact 7x8 mm footprint with an exposed pad (EP) that bonds the die substrate to PCB copper, lowering thermal resistance and improving high-temperature performance. Configuration is via SPI or a parallel mode-select interface, allowing trade-offs between sample rate, channel count, and output width. Typical applications include diversity RF receivers, MIMO/Multi-IF downconverters, advanced wireless base stations, broadband wireless local loops, and portable test instrumentation. The quad-channel, simultaneous-sampling architecture is particularly well-suited to I/Q capture paths where phase coherence between channels is critical. When designing in this device, allocate adequate ground returns and a solid ground pour on layer 2 beneath the QFN, and follow the analog input network shown in the datasheet (typically a small series damping resistor plus shunt capacitance) to control charge kickback at high input frequencies. Decouple AVDD and DVDD separately with low-ESR ceramics near the pins. This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving the design engineer a single, decision-ready reference.
LTC2180CUP - 16-Bit 25Msps Dual ADC, Low Power | Analog Devices
The Analog Devices LTC2180CUP is a 16-bit, 25Msps low-power dual simultaneous-sampling analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) exposed-pad package. Each channel delivers 76.8dB SNR and 90dB SFDR at 5MHz input, achieving -110dB channel crosstalk while consuming only 75mW per channel. The pipelined architecture includes integrated CMOS or LVDS output modes, internal reference, and pin-selectable input ranges, eliminating the need for external buffer circuitry in most applications. According to the Analog Devices datasheet (218210f), the part is specified from -40C to +85C and is targeted at demanding communications applications where wide dynamic range signals must be digitized accurately. A pipelined ADC is a converter topology that processes the analog input through cascaded low-resolution stages, producing a high-resolution digital word at high conversion rates with relatively low latency. The dual-channel configuration places two complete ADC cores on a single substrate so each can be sampled on the same clock edge, enabling accurate I/Q or differential acquisition. Compared with sigma-delta ADCs, pipeline converters offer substantially wider input bandwidths (here 400MHz analog input) at the cost of somewhat higher noise spectral density. This makes the LTC2180 a representative entry in the precision pipeline ADC segment used in instrumentation, test equipment, communications transceivers, and medical imaging front-ends. Key features include selectable 1.5Vpp or 2Vpp input ranges, an internal high-precision reference that eliminates an external reference IC, optional CMOS or LVDS digital outputs for flexible FPGA/ASIC interfacing, and a low-jitter clock multiplier that allows operation with a low-frequency external reference clock. The LVDS path supports DDR mode for tighter board-level timing margins at high sample rates. Internally, the device uses a 16-stage pipeline architecture with proprietary calibration to maintain linearity over temperature. The exposed thermal pad on the QFN package reduces theta-JA to approximately 21C/W on a 4-layer JEDEC test board, enabling reliable operation at full sample rate without forced-air cooling. Power-down current drops below 1uA per channel, making the device attractive for portable or battery-backed multi-channel instruments. Typical applications include multi-antenna software-defined radio (SDR) receivers, multi-carrier cellular base-station observation, simultaneous-sampling data acquisition modules, ultrasound beamforming front-ends, and high-end test-and-measurement instruments. Engineers typically deploy the part behind a low-noise differential driver such as the LTC6400 or ADA4937 to fully exploit its dynamic range. When designing with this device, pay close attention to PCB layout for the analog inputs and clock lines: the exposed pad must be soldered to a continuous ground plane to achieve the specified thermal and electrical performance. Use length-matched LVDS routing to the host FPGA to avoid timing skew between channels and to preserve the 90dB SFDR. This page synthesizes distributor pricing, drop-in alternatives (LTC2181CUP, LTC2155CUP-12), and practical design notes not found in the manufacturer datasheet alone, including I/Q sample-rate planning and reference-decoupling guidance.
LTC2180IUP - 16-Bit 25Msps Dual ADC | Analog Devices
The Analog Devices LTC2180IUP is a 16-bit, 25Msps low-power dual simultaneous-sampling analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm, exposed pad) package. It provides two fully differential input channels with pipelined architecture, 77 dB SNR, and 90 dB spurious-free dynamic range, optimized for demanding communications, instrumentation, and high-speed signal-acquisition designs. Background Knowledge: An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog signals into discrete digital codes. Dual ADCs contain two independent converter channels that sample simultaneously, which is essential when the relative phase between two signals carries information (for example, I/Q baseband signals in a radio receiver, or paired sensor channels in sonar and vibration analysis). The LTC2180 family sits within the broader hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Key features include 25 Msps sampling per channel, simultaneous sampling of both inputs, ultralow jitter of 0.07 ps RMS that enables IF undersampling, an internal common-mode reference buffer, and a flexible CMOS/LVDS digital output bus. The pipelined architecture delivers low latency while maintaining 16-bit resolution at full throughput. Total power dissipation is approximately 250 mW per channel at full rate. Typical applications include diversity receivers and I/Q digitizers in software-defined radio, multi-channel ultrasound front ends, precision data acquisition, wideband spectrum analyzers, and medical imaging subsystems. The wide input bandwidth and excellent SFDR make it suitable for direct-IF sampling. Design consideration: because both channels share a common clock and reference, layout must keep analog and digital grounds separated under the exposed pad. Aggressive LC filtering on the analog AVDD supply is critical to maintain SNR at high input frequencies. This page synthesizes distributor pricing, drop-in same-package alternatives from the same LTC family, and practical design notes not consolidated in the manufacturer datasheet, providing decision-ready information for engineers selecting a 16-bit dual ADC for a multi-channel signal chain.
LTC2181IUP - 16-Bit 40Msps Dual ADC, DDR LVDS | Analog Devices
The Analog Devices LTC2181IUP is a 16-bit, 40 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) with DDR LVDS outputs, housed in a 64-pin QFN (9x9 mm) package. It features two ADC channels sampling at the same instant, 77 dBFS signal-to-noise ratio (SNR) at 5 MHz input, and 90 dBFS spurious-free dynamic range (SFDR), all from a single 1.8 V analog supply and an optional LVDS swing supply. The device is specified over the industrial temperature range of -40C to +85C. An ADC (Analog-to-Digital Converter) is a data converter that samples continuous analog voltage signals and produces discrete digital codes. Within the broader semiconductor hierarchy, the LTC2181IUP belongs to the high-speed ADC family, which is itself a sub-category of data converters, sitting alongside DACs (Digital-to-Analog Converters) and CODECs. High-speed pipeline ADCs like the LTC2181 are the workhorse of communications, test and measurement, and defense signal chains where wide analog bandwidth and high dynamic range are required. Key features include integrated bypass capacitance to reduce PCB complexity, selectable input ranges of 1 Vp-p to 2 Vp-p, an internal duty-cycle stabilizer that corrects for clock duty-cycle distortion, and a low-jitter clock receiver that accepts CMOS, LVDS, or sine-wave inputs. Each channel is independently controlled via a 3-wire SPI-compatible serial interface, allowing per-channel gain, offset, and phase calibration without external trim. The 64-lead QFN package with an exposed pad provides a thermal resistance (theta_JC) suitable for the device's low 100 mW per channel power dissipation. The LTC2181's pipelined architecture is built around 16 internal stages with error correction, and its DDR LVDS digital interface transmits two data bits per clock cycle, halving the number of required output traces and easing PCB routing. The combination of low jitter (< 70 fs), high SNR, and selectable LVDS swing (350 mV or 700 mV) makes it well suited for driving FPGAs and ASICs over short board-to-board links. Typical applications include cellular base-station receive paths, multiband, multimode digital receivers, antenna array processing, communications test equipment, and high-end imaging systems such as medical ultrasound and non-destructive flaw detection. The dual simultaneous-sampling architecture is particularly important for I/Q demodulation and for any system that requires phase-coherent acquisition of two signals. When designing with the LTC2181IUP, place the 1.8 V analog decoupling capacitors within 5 mm of the AVDD pins and bond the exposed pad to a clean ground plane to keep digital switching currents out of the analog return path. The DDR LVDS output timing is referenced to the rising clock edge; be sure to use the same source-matched impedance (100 ohm differential) on all data and clock pairs to avoid inter-symbol jitter. This page synthesizes distributor pricing, drop-in same-family alternatives (LTC2180, LTC2182), and practical layout guidance that is not contained in the bare manufacturer datasheet.
LTC2182CUP - 16-Bit 65Msps Dual ADC, 77dB SNR | Analog Devices
The Analog Devices LTC2182CUP is a 16-bit, 65 Msps low-power dual simultaneous-sampling analog-to-digital converter (ADC) housed in a 64-pin QFN (UP) 9x9 mm package. It delivers 77 dB SNR and 90 dB spurious-free dynamic range (SFDR) with ultralow 0.07 ps RMS jitter, enabling undersampling of high-IF signals with excellent linearity. The dual-channel pipelined architecture drives a total IC power dissipation under 230 mW at 65 Msps, making it suitable for thermally-constrained multi-channel systems. An ADC (analog-to-digital converter) is a data-converter IC that samples continuous analog signals and produces quantized digital codes, and the pipelined sub-class achieves high sampling rates by cascading multiple low-resolution stages. Within the broader hierarchy, the LTC2182 sits as: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. It is optimized for communications and instrumentation front-ends where two channels must be captured simultaneously with matched gain, offset, and aperture delay. Key features include a 1.7 V to 1.9 V analog supply (1.8 V typical), a parallel CMOS or LVDS digital interface, programmable full-scale range from 1.0 V to 2.0 V peak-to-peak, and an optional external reference. Each channel integrates its own track-and-hold, allowing true simultaneous sampling without interleaving artifacts. Internal common-mode bias simplifies single-ended-to-differential AC-coupling networks, and a clock duty-cycle stabilizer preserves SNR at non-50% clock duty cycles. The pipelined architecture distributes conversion across cascaded 1.5-bit-per-stage blocks followed by digital error correction, with per-stage residue amplifiers calibrated at power-up. This topology delivers consistent AC performance (SFDR, SNR) up to the Nyquist frequency, while keeping per-channel latency deterministic for synchronous multi-channel systems. Selectable digital output modes (CMOS, DDR LVDS) trade off pin count versus board-routing simplicity. Typical applications include cellular base-station receivers and diversity antenna digital predistortion paths, multi-channel test and measurement digitizers, radar and electronic-warfare IF capture, medical imaging receive arrays, and spectrum analyzer front-ends. The 0.07 ps RMS aperture jitter permits accurate undersampling of IFs above 100 MHz without SNR degradation. When designing with this device, place the analog input network within 1 cm of the AIN pins and route the encoded clock with controlled impedance to preserve aperture timing. Power-supply decoupling requires a 10 uF bulk plus 0.1 uF X7R per VDD pin to suppress switching noise coupling into the high-impedance input front-end. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone manufacturer datasheet.
LTC2182IUP - 16-Bit 65Msps Dual ADC | Analog Devices
The Analog Devices LTC2182IUP is a 16-bit, 65 Msps, low-power, dual-channel simultaneous-sampling analog-to-digital converter (ADC) housed in a 64-pin QFN (9 mm x 9 mm) exposed-pad package. It features two matched pipeline ADC cores, on-chip DDR LVDS or CMOS outputs, and AC performance that delivers 77 dB SNR and 90 dB spurious-free dynamic range (SFDR), making it well suited for digitizing high-frequency, wide-dynamic-range signals in communications, instrumentation, and defense systems. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog waveform and converts it into a discrete digital code word. In the broader IC taxonomy, dual pipeline ADCs sit between general-purpose successive-approximation-register (SAR) ADCs and high-speed flash converters; the pipeline architecture enables sample rates from tens to hundreds of Msps while maintaining 14-16 bit resolution. The LTC2182IUP belongs to the family of dual ADC ICs that simultaneously sample two channels - critical for I/Q signal processing, diversity receivers, and beamforming where channel-to-channel phase matching must be preserved. Key features of the LTC2182IUP include a programmable LVDS/CMOS output mode, internal clock duty-cycle stabilizer, digital randomizer and dither, and pin-selectable full-scale input range between 1 Vp-p and 2 Vp-p. The integrated common-mode bias and on-chip reference simplify board design, while the selectable low-power and low-noise operating modes let designers trade idle current against dynamic range at the application level. Internally, each channel uses a 16-stage switched-capacitor pipeline fronted by a wide-bandwidth differential sample-and-hold amplifier. The digital back-end includes a 16-bit flash error-correction block plus configurable output serializers that can drive either CMOS or DDR LVDS, easing interfacing with FPGAs and dedicated ASICs. Typical applications for the LTC2182IUP include direct-IF sampling diversity receivers, multi-antenna software-defined-radio (SDR) front ends, vector signal analyzers, time-interleaved digital oscilloscopes, and medical imaging receivers. Communications system designers value the 90 dB SFDR for clean decoding of multi-carrier waveforms such as LTE, 5G NR, and DVB-S2X. A primary design consideration is LVDS-versus-CMOS output trade-off: LVDS provides up to 65 Msps with robust noise immunity across backplanes, while single-wire CMOS output halves the I/O count at the expense of speed when lower sample rates suffice. Always tie the exposed pad (EP) directly to a low-impedance ground plane - the EP is the primary thermal and ground return for both ADC channels. This page synthesizes distributor pricing, drop-in package-matched alternatives, and practical layout notes that extend beyond the manufacturer datasheet.
LTC2183CUP - 16-Bit 80Msps Dual ADC Low Power QFN-64 | Analog Devices
The Analog Devices LTC2183CUP is a 16-bit, 80Msps dual-channel simultaneous-sampling low-power analog-to-digital converter (ADC) housed in a 64-lead QFN (UP) 9x9 mm package with exposed pad. The device delivers 76.8 dB SNR and 90 dB SFDR with ultra-low 0.07 psRMS aperture jitter, making it well suited for digitizing wide-dynamic-range, high-frequency signals. A dual pipelined ADC is a converter architecture that uses multiple low-resolution stages in series, with each stage sampling and converting a portion of the input before passing residue to the next stage; digital error correction aligns the bits. Dual ADCs are commonly used in diversity receivers, I/Q demodulation, and medical imaging where two correlated channels must be digitized on the same clock edge. The LTC2183 family belongs to the broader converter IC category, sitting between analog front-end signal conditioning and downstream DSP/FPGA logic. Key features include user-selectable LVDS / DDR LVDS / CMOS output modes, a parallel low-voltage CMOS port option, an SPI port for configuration, internal dither to improve small-signal linearity, and a clock duty-cycle stabilizer. Total power consumption is approximately 390 mW at 80 Msps, far below competing dual ADCs. Input range is 2 Vp-p (fully differential) with an internal PGA. Typical applications include communications receivers, basestation diversity channels, I/Q demodulators, portable instrumentation, medical imaging front-ends, and non-destructive ultrasonic testing. The exposed-pad QFN-64 package enables low thermal resistance for sustained operation. When designing in the LTC2183CUP, pay close attention to differential input network design, layout of the clock tree, and decoupling strategy on both AVDD and DVDD rails to realize the full 76.8 dB SNR specification.
LTC2184IUP - 16-Bit 105Msps Dual ADC, 64-QFN | Analog Devices
The Analog Devices LTC2184IUP is a 16-bit, 105 Msps dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 64-pin QFN (9x9) package. It features two differential or single-ended analog inputs, an integrated high-performance reference, and on-chip CMOS or LVDS digital outputs, making it suitable for communications, medical imaging, and instrumentation front ends. A pipelined ADC (also called a pipeline converter) is a type of analog-to-digital converter that resolves an input sample through a cascade of low-resolution stages, each producing one or more output bits. Pipelined ADCs offer a balanced trade-off between speed, resolution, and power: they sample at tens to hundreds of Msps while maintaining 12- to 16-bit resolution, making them the dominant architecture in communications infrastructure, radar, and IF-sampling applications. Within the broader power-management and signal-chain hierarchy, a high-speed ADC like the LTC2184 sits downstream of an analog front-end (amplifier, anti-alias filter) and upstream of an FPGA or ASIC that performs digital signal processing. The LTC2184 delivers 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR), with ultralow 0.07 ps RMS aperture jitter that allows accurate undersampling of IF frequencies. According to the Analog Devices datasheet, this dual ADC supports CMOS, LVDS, or DDR LVDS digital output modes to ease interfacing with FPGAs and ASICs, and offers a low-power shutdown mode for power-sensitive designs. Typical applications include cellular base-station receivers, software-defined radio, MRI gradient amplifiers, radar signal conditioning, and high-speed data acquisition cards. The wide input bandwidth also makes it appropriate for cable infrastructure and spectrum analyzer designs. When laying out the PCB, treat each analog input as a 50 ohm or 100 ohm differential transmission line and use a solid ground plane beneath the 64-QFN exposed pad to minimize coupling and to keep the device within its thermal envelope. Always drive the encode clock with a low-jitter source; any clock jitter directly adds to the aperture uncertainty and degrades SNR. This page synthesizes distributor pricing, drop-in same-family alternatives (LTC2185IUP, LTC2183IUP), and practical layout guidance that is not consolidated in the manufacturer datasheet PDF alone.
LTC2188CUP - 16-Bit 20Msps Dual ADC | Analog Devices
The Analog Devices LTC2188CUP is a two-channel simultaneous-sampling 16-bit analog-to-digital converter designed for digitizing high-frequency, wide-dynamic-range signals, and is offered in a 64-pin QFN (UP) package. It samples at up to 20 Msps per channel with a pipelined architecture, delivering 77 dB SNR and 90 dB spurious-free dynamic range (SFDR) for communications, instrumentation, and medical imaging front-ends. The converter integrates low-jitter clock conditioning, CMOS or DDR LVDS digital output modes, and configurable full-scale input ranges. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes at a sample rate determined by an external clock. Pipelined ADCs like the LTC2188CUP use multiple low-resolution stages to digitize one input sample per clock cycle after an initial pipeline latency, achieving a balance of high sample rate, moderate resolution, and low power consumption. They sit within the broader hierarchy of signal chain components: ADC -> data converter -> mixed-signal IC -> semiconductor, and are typically paired with low-noise front-end amplifiers, anti-alias filters, and FPGA or ASIC capture logic. Key features of the LTC2188CUP include dual simultaneous 20 Msps channels, 16-bit resolution, 77 dB SNR at 10 MHz input, 90 dB SFDR, support for CMOS and DDR LVDS output interfaces, an internal sample-and-hold, and programmable analog input span. Integrated digital features such as data-ready outputs and pattern generation simplify board bring-up and FPGA/ASIC handshake design. The part is offered in commercial (C) and industrial/extended temperature grades. The LTC2188CUP uses a multi-stage pipelined core with proprietary dithering techniques that linearize the transfer function and improve small-signal SFDR. A differential input architecture rejects common-mode noise and even-order harmonics, while on-chip bias generation reduces the external component count. The device consumes roughly 65 mW per channel at 20 Msps and includes power-down modes for portable or multi-channel systems where thermal budget is constrained. Typical applications include digital oscilloscopes and wideband data acquisition, communications receivers and software-defined radio (SDR) front-ends, medical ultrasound beamformers, and industrial imaging systems. The dual-channel simultaneous sampling makes the LTC2188CUP particularly well-suited to I/Q baseband digitizers and multi-antenna diversity receivers where channel-to-channel timing alignment is critical. When designing with the LTC2188CUP, pay close attention to the analog input network: a wideband, differential, low-distortion front-end (such as the ADA4932 or LTC6406) is typically required to preserve the converter's 90 dB SFDR. Decouple the AVDD and DVDD rails with separate low-ESR ceramic capacitors placed as close as possible to the package pins, and route differential pairs with controlled 100-ohm impedance on the PCB. This page synthesizes verified distributor pricing, drop-in alternatives drawn from the LTC2188 family (LTC2185, LTC2186, LTC2187) plus pin-compatible ADI 16-bit ADCs, and practical design notes not found in the manufacturer datasheet alone.
LTC2188IUP - 16-Bit 20Msps Dual ADC | Analog Devices
The Analog Devices LTC2188IUP is a 16-bit, 20 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 64-lead QFN (9 x 9 mm) package with exposed pad. Each channel delivers 77 dB SNR and 90 dB spurious-free dynamic range, making the part well-suited for digitizing high-frequency, wide-dynamic-range signals in demanding communications and instrumentation systems. The IUP suffix denotes the industrial-grade -40C to +85C operating range required for telecom baseband, multi-standard radio and direct-IF conversion paths. What is a dual simultaneous-sampling ADC? A dual simultaneous-sampling ADC is a category of data converter that captures two analog input channels through independent sample-and-hold circuits driven by a common clock, ensuring channel-to-channel skew of picoseconds rather than nanoseconds. In the broader taxonomy, the LTC2188 family sits within successive-approximation / pipelined ADCs -> data converters -> mixed-signal ICs -> signal chain components. The simultaneous-sample property matters whenever phase or IQ information must be preserved between channels (communications, beamforming, predistortion). Key features of the LTC2188IUP include a single 1.8 V analog supply, LVDS or CMOS configurable digital outputs, optional internal dither to improve SFDR at small input levels, and a low-jitter clock input that relaxes the noise requirements of the front-end PLL. The device integrates input kick-back suppression and selectable input bandwidth, allowing direct connection to wideband IF signals without a front-end buffer. Power dissipation scales gracefully with sample rate, allowing the user to throttle clocks for low-power idle states. Typical applications for the LTC2188IUP span LTE/4G/5G baseband digitizers, multi-standard software-defined radios, multi-channel data acquisition front-ends for instrumentation and beamforming arrays used in radar and medical imaging prototypes. Designers who must interface to an FPGA typically use the LVDS output mode to preserve timing margins at 20 Msps on long board traces. When laying out a board for the LTC2188IUP, keep analog and digital ground returns joined only at the exposed pad, and place the 0.1 microfarad ceramic decoupling capacitors within 1 mm of each supply pin. The 64-QFN exposed pad must be soldered to a continuous ground plane to keep junction temperature within the 31 C/W theta_JA budget; inadequate thermal connection will degrade AC linearity.