RTAX2000S-1CGS624EV vs RTAX2000SL-CGS624V So sánh
So sánh chi tiết song song của RTAX2000S-1CGS624EV bằng Microchip Technology và RTAX2000SL-CGS624V bằng Microchip Technology. So sánh các thông số quan trọng, thông số điện tử, gói gọn, trạng thái vòng đời, giá cả và khả năng cung cấp để xác định linh kiện tốt nhất cho yêu cầu thiết kế của bạn.
Microchip Technology
RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624EV ✓ Hoạt độngMicrochip Technology
RTAX2000SL-CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000SL-CGS624V ✓ Hoạt độngSo sánh thông số kỹ thuật
| Tham số | RTAX2000S-1CGS624EV | RTAX2000SL-CGS624V |
|---|---|---|
| Thương hiệu | Microchip Technology | Microchip Technology |
| Danh mục | FPGA & CPLD | FPGA & CPLD |
| Trạng thái vòng đời | Hoạt động | Hoạt động |
| System Gates | 2,000,000 | — |
| Logic Cells (CLBs) | 21504 | 21504 |
| Total Cells | 32256 | — |
| Additional ASIC Equivalent Gates | 250000 | — |
| Hộp | 624-pin Ceramic Column Grid Array (CGA-624 / CCGA624) | CG624 ceramic package |
| Core Supply Voltage | 1.5 V nominal (1.425 V to 1.575 V) | [DATA_NEEDED: core supply voltage] |
| Nhiệt độ hoạt động | -55C to +125C | [DATA_NEEDED: operating temperature range] |
| Process Technology | 0.15 um CMOS | — |
| Maximum Frequency | 649 MHz | — |
| Logic Family | CMOS | — |
| SEU Immunity | SEU-hardened registers, immune to single-event upsets to specified LET threshold | — |
| SEU Rate | < 10-10 errors/bit-day | — |
| Configuration | One-time programmable anti-fuse, live at power-up, single chip | One-time programmable antifuse, live at power-up |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | 540 kbits with optional EDAC protection |
| Kiểu lắp đặt | Surface Mount | — |
| Product Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | — |
| Thermal Resistance Basis | JEDEC JESD51 simulation conditions (per datasheet) | — |
| I/O Supply Voltage | [DATA_NEEDED: I/O bank voltage] | [DATA_NEEDED: I/O supply voltage] |
| Maximum User I/O | [DATA_NEEDED: user I/O count] | — |
| Trạng thái RoHS | [DATA_NEEDED: RoHS status] | — |
| Equivalent System Gates | — | 2000000 |
| Technology | — | CMOS antifuse (nonvolatile) |
| User I/Os (maximum) | — | 684 |
| Total Ionizing Dose (TID) | — | 300 krad (Si) functional / 200 krad (Si) parametric |
| Single-Event Upset Rate | — | Less than 1E-10 errors per bit-day |
| Embedded SRAM Features | — | Built-in FIFO control logic |
| Clock Architecture | — | Segmentable clock structures |
| Routing | — | Chip-wide highway routing, carry logic |
| Family | — | RTAX-S/SL Radiation-Tolerant FPGA |
| Application Domain | — | Space-flight systems |
| Speed Grade | — | [DATA_NEEDED: speed grade] |
| System Frequency (typical) | — | [DATA_NEEDED: system frequency] |