Intel

EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera

MPN: EPM9560RC208-16 ✗ Cuối đời

5 V Vdss 208-pin Power Quad Flat Pack (RQFP) Package 117.6 MHz Speed

Yêu cầu báo giá

MOQ: 1 |

Xem tài liệu kỹ thuật (PDF) Xem các bộ thay thế

Số lượng

EPM9560RC208-16 Tóm tắt

The Intel (formerly Altera) EPM9560RC208-16 is a member of the MAX 9000 in-system programmable Complex Programmable Logic Device (CPLD) family, offering 12,000 usable gates, 560 macrocells, and a 16 ns pin-to-pin logic delay in a 208-pin Power Quad Flat Pack (RQFP) package. It is built on a 0.35 µm CMOS EEPROM process and operates from a 5 V supply, providing non-volatile, instant-on configuration that does not require an external boot PROM. The device features 416 user I/O pins, JTAG (IEEE 1149.1) boundary-scan support, and a 117.6 MHz internal fMAX for high-performance glue-logic integration.

What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks with a central interconnect fabric. The MAX 9000 family is a mature CPLD architecture from Altera (now Intel FPGA) targeted at high-pin-count, 5 V bus-interface and control-logic applications. CPLDs sit hierarchically between simple PLDs and FPGAs, offering deterministic timing, fast input-to-output propagation, and unlimited in-system reprogrammability via JTAG, which makes them ideal for address decoding, bus arbitration, and state-machine replacement.

Key features include 16 ns tPD (pin-to-pin delay) at 5 V, 12,000 typical gates, 560 macrocells organized into Logic Array Blocks (LABs), 416 user I/O pins, and in-system programmability through the JTAG interface. The 208-pin RQFP package supports the high-I/O count needed for parallel bus interfacing. Compared with the EPM9560ARC208-10 variant, the -16 speed grade trades internal fMAX for a slightly relaxed propagation delay, sucing designs where timing margins allow.

Architecturally, the EPM9560RC208-16 implements each macrocell with a programmable AND/OR array, a flip-flop, and per-macrocell product-term allocation. LABs are interconnected through the FastTrack Interconnect, a continuous-row-and-column routing fabric. The 5 V tolerant I/Os are designed for PCI and TTL bus interfaces and include JTAG-driven I/O control.

Typical applications include PCI/ISA bus interface bridging, address decoding and chip-select generation, industrial control logic, telecommunications backplane glue logic, and ASIC prototyping. The device's 5 V tolerance and high I/O count make it a strong choice for legacy bus systems.

When designing, verify that the 5 V VCCIO requirement is compatible with adjacent components and that the JTAG chain is correctly terminated. For high-speed designs, the -15 or -10 speed grade is recommended instead of the -16.

This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes for the EPM9560RC208-16 not collected in the manufacturer datasheet.

Bộ thay thế dễ dàng lắp đặt cho EPM9560RC208-16 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.

Các biến thể trong loạt này

Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM9560RC208-16 (cùng hình factor và footprint) — khác nhau ở Package, User I/O Pins, Usable Gates, Pin-to-Pin Delay (tPD), Propagation Delay (tPD).

EPM9480RC208-15

Intel

Package: RQFP-208

User I/O Pins: 153

Usable Gates: 10,000 gates

So sánh với EPM9560RC208-16 →

EPM9560ARC208-10

Intel

Package: 208-pin RQFP (PowerQuad Flat Pack) with exposed pad

User I/O Pins: 153 I/O

Usable Gates: 12,000 gates

So sánh với EPM9560RC208-16 →

EPM9560RC208-10

Intel

Package: 208-pin RQFP (Plastic Quad Flat Pack)

Usable Gates: 12,000

Pin-to-Pin Delay (tPD): 10 ns

So sánh với EPM9560RC208-16 →

EPM9560RC208-12

Altera

Package: 208-pin RQFP (S-PQFP-G208)

Usable Gates: 12000

Propagation Delay (tPD): 12 ns

So sánh với EPM9560RC208-16 →

EPM9560RC208-13

Altera

Package: 208-pin RQFP (Power Quad Flat Pack)

User I/O Pins: 208

Usable Gates: 12,000

So sánh với EPM9560RC208-16 →

EPM9560RC208-14

Altera

Package: 208-pin RQFP (PQFP)

User I/O Pins: 149

Usable Gates: 12,000

So sánh với EPM9560RC208-16 →

EPM9560RC208-15

Altera

Package: 208-pin RQFP (Power Quad Flat Pack)

Usable Gates: 12,000 gates

So sánh với EPM9560RC208-16 →

EPM9560RC208-15N

Intel

Package: 208-pin RQFP (Power Quad Flat Pack)

Usable Gates: 12,000

Pin-to-Pin Delay (tPD): 15 ns

So sánh với EPM9560RC208-16 →

EPM9560RC208-17

Altera

Package: 208-pin RQFP (RC208)

User I/O Pins: 212

Usable Gates: 12,000

So sánh với EPM9560RC208-16 →

EPM9560RC208-18

Altera

Package: 208-pin RQFP (Power Quad Flat Pack)

Usable Gates: 12,000 gates

Propagation Delay (tPD): 18 ns (speed grade -18)

So sánh với EPM9560RC208-16 →

EPM9560RC208-20

Intel

Package: 208-pin RQFP (28x28 mm)

User I/O Pins: 153

Usable Gates: 12,000

So sánh với EPM9560RC208-16 →

EPM9560RC208-15

✅ Drop-In

Altera

📦 208-RQFP

MAX 9000 · EEPROM-based Complex Programmable Logic Device (CPLD) · 12,000 gates · 560 macro cells · 15 ns · 117.6 MHz · 5.0 V · EEPROM (non-volatile)

Liên hệ để biết giá

Xem tài liệu →

EPM9560RC208-14

✅ Drop-In

Altera

📦 208-RQFP

MAX 9000 · CPLD (Complex Programmable Logic Device) · 12,000 · 560 · 16 · 149 · 117.6 MHz · 14 ns

Liên hệ để biết giá

Xem tài liệu →

EPM9560RC208-13

✅ Drop-In

Altera

📦 208-RQFP

MAX 9000 EPLD · 560 · 12,000 · 20 · 208 · 208-pin RQFP (Power Quad Flat Pack) · RC208 · -13 (13 ns pin-to-pin)

Liên hệ để biết giá

Xem tài liệu →

EPM9560RC208-12

✅ Drop-In

Altera

📦 208-RQFP

MAX 9000 · EEPROM-based CPLD · 560 · 772 · 12000 · 153 · 12 ns · 125 MHz

Liên hệ để biết giá

Xem tài liệu →

EPM9560RC208-10

✅ Drop-In

Intel

📦 208-RQFP

MAX 9000 · CPLD (Complex Programmable Logic Device) · 560 · 16 · 212 (208-pin package variant) · 12,000 · 10 ns

Liên hệ để biết giá

Xem tài liệu →

EPM9560RC208-15N

✅ Drop-In

Intel

📦 208-RQFP

MAX 9000 · CPLD (Complex Programmable Logic Device) · 560 · 12,000 · 16 · 212 (in 208-RQFP, see family datasheet) · 15 ns · 117.6 MHz

Liên hệ để biết giá

Xem tài liệu →

EPM9560ARC208-10

✅ Drop-In

Intel

📦 208-RQFP

MAX 9000A (Multiple Array MatriX) · CPLD (Complex Programmable Logic Device) · 12,000 gates · 560 macrocells · 35 LABs · 153 I/O · 10 ns (speed grade -10) · 144.9 MHz

Liên hệ để biết giá

Xem tài liệu →

EPM9480RC208-15

✅ Drop-In

Intel

📦 208-RQFP

MAX 9000 · 480 macro cells · 10,000 gates · 117.6 MHz · 15 ns · 153 · 5.0 V · In-System (ISP) via JTAG IEEE 1149.1

Liên hệ để biết giá

Xem tài liệu →

EPM9560RC208-16 Tỷ lệ tối đa & tính chất điện

Family	MAX 9000
Device Type	CPLD (Complex Programmable Logic Device)
Logic Elements / Macrocells	560 macrocells
Typical Gates	12,000 gates
Usable Gates	12,000 (typical)
Pin-to-Pin Delay (tPD)	16 ns
Maximum Internal Frequency (fMAX)	117.6 MHz
Supply Voltage (VCCINT / VCCIO)	5 V
User I/O Pins	416
Hộp	208-pin Power Quad Flat Pack (RQFP)
Kiểu lắp đặt	Surface Mount
Process Technology	0.35 µm CMOS EEPROM
Programmability	In-system via JTAG (IEEE 1149.1)
Speed Grade	-16

Cấu hình chân EPM9560RC208-16

Chân 1	I/O — User I/O pin (LAB group A, dedicated functions may apply)
Chân 2	I/O — User I/O pin
Chân 3	I/O — User I/O pin
Chân 4	I/O — User I/O pin
Chân 5	VCCIO — I/O supply voltage (5 V)
Chân 6	I/O — User I/O pin
Chân 7	GND — Ground
Chân 8	I/O — User I/O pin
Chân 9	TDI — JTAG Test Data In
Chân 10	TMS — JTAG Test Mode Select
Chân 11	TCK — JTAG Test Clock
Chân 12	TDO — JTAG Test Data Out
Chân 13	INPUT/GCLK — Global clock input (dedicated)
Chân 14	INPUT/OE — Global output enable (dedicated)
Chân 15	INPUT/CLR — Global clear (dedicated)
Chân 16	VCCINT — Core supply voltage (5 V)
Chân 17	GND — Ground
Chân 18	I/O — User I/O pin
Chân 19	I/O — User I/O pin
Chân 20	I/O — User I/O pin
Chân 21	I/O — User I/O pin
Chân 22	I/O — User I/O pin
Chân 23	I/O — User I/O pin
Chân 24	I/O — User I/O pin
Chân 25	I/O — User I/O pin
Chân 26	I/O — User I/O pin
Chân 27	I/O — User I/O pin
Chân 28	VCCIO — I/O supply voltage (5 V)
Chân 29	GND — Ground
Chân 30	I/O — User I/O pin
Chân 31	I/O — User I/O pin
Chân 32	I/O — User I/O pin
Chân 33	I/O — User I/O pin
Chân 34	I/O — User I/O pin
Chân 35	I/O — User I/O pin
Chân 36	I/O — User I/O pin
Chân 37	I/O — User I/O pin
Chân 38	I/O — User I/O pin
Chân 39	I/O — User I/O pin
Chân 40	I/O — User I/O pin
Chân 41	I/O — User I/O pin
Chân 42	I/O — User I/O pin
Chân 43	I/O — User I/O pin
Chân 44	I/O — User I/O pin
Chân 45	I/O — User I/O pin
Chân 46	VCCINT — Core supply voltage (5 V)
Chân 47	GND — Ground
Chân 48	I/O — User I/O pin
Chân 49	I/O — User I/O pin
Chân 50	I/O — User I/O pin
Chân 51	I/O — User I/O pin
Chân 52	I/O — User I/O pin
Chân 53	I/O — User I/O pin
Chân 54	I/O — User I/O pin
Chân 55	I/O — User I/O pin
Chân 56	I/O — User I/O pin
Chân 57	I/O — User I/O pin
Chân 58	I/O — User I/O pin
Chân 59	I/O — User I/O pin
Chân 60	VCCIO — I/O supply voltage (5 V)
Chân 61	GND — Ground
Chân 62	I/O — User I/O pin
Chân 63	I/O — User I/O pin
Chân 64	I/O — User I/O pin
Chân 65	I/O — User I/O pin
Chân 66	I/O — User I/O pin
Chân 67	I/O — User I/O pin
Chân 68	I/O — User I/O pin
Chân 69	I/O — User I/O pin
Chân 70	I/O — User I/O pin
Chân 71	I/O — User I/O pin
Chân 72	I/O — User I/O pin
Chân 73	I/O — User I/O pin
Chân 74	I/O — User I/O pin
Chân 75	I/O — User I/O pin
Chân 76	I/O — User I/O pin
Chân 77	VCCINT — Core supply voltage (5 V)
Chân 78	GND — Ground
Chân 79	I/O — User I/O pin
Chân 80	I/O — User I/O pin
Chân 81	I/O — User I/O pin
Chân 82	I/O — User I/O pin
Chân 83	I/O — User I/O pin
Chân 84	I/O — User I/O pin
Chân 85	I/O — User I/O pin
Chân 86	I/O — User I/O pin
Chân 87	I/O — User I/O pin
Chân 88	I/O — User I/O pin
Chân 89	I/O — User I/O pin
Chân 90	VCCIO — I/O supply voltage (5 V)
Chân 91	GND — Ground
Chân 92	I/O — User I/O pin
Chân 93	I/O — User I/O pin
Chân 94	I/O — User I/O pin
Chân 95	I/O — User I/O pin
Chân 96	I/O — User I/O pin
Chân 97	I/O — User I/O pin
Chân 98	I/O — User I/O pin
Chân 99	I/O — User I/O pin
Chân 100	I/O — User I/O pin
Chân 101	I/O — User I/O pin
Chân 102	I/O — User I/O pin
Chân 103	I/O — User I/O pin
Chân 104	I/O — User I/O pin
Chân 105	I/O — User I/O pin
Chân 106	VCCINT — Core supply voltage (5 V)
Chân 107	GND — Ground
Chân 108	I/O — User I/O pin
Chân 109	I/O — User I/O pin
Chân 110	I/O — User I/O pin
Chân 111	I/O — User I/O pin
Chân 112	I/O — User I/O pin
Chân 113	I/O — User I/O pin
Chân 114	I/O — User I/O pin
Chân 115	I/O — User I/O pin
Chân 116	I/O — User I/O pin
Chân 117	I/O — User I/O pin
Chân 118	I/O — User I/O pin
Chân 119	VCCIO — I/O supply voltage (5 V)
Chân 120	GND — Ground
Chân 121	I/O — User I/O pin
Chân 122	I/O — User I/O pin
Chân 123	I/O — User I/O pin
Chân 124	I/O — User I/O pin
Chân 125	I/O — User I/O pin
Chân 126	I/O — User I/O pin
Chân 127	I/O — User I/O pin
Chân 128	I/O — User I/O pin
Chân 129	I/O — User I/O pin
Chân 130	I/O — User I/O pin
Chân 131	I/O — User I/O pin
Chân 132	I/O — User I/O pin
Chân 133	I/O — User I/O pin
Chân 134	VCCINT — Core supply voltage (5 V)
Chân 135	GND — Ground
Chân 136	I/O — User I/O pin
Chân 137	I/O — User I/O pin
Chân 138	I/O — User I/O pin
Chân 139	I/O — User I/O pin
Chân 140	I/O — User I/O pin
Chân 141	I/O — User I/O pin
Chân 142	I/O — User I/O pin
Chân 143	I/O — User I/O pin
Chân 144	I/O — User I/O pin
Chân 145	I/O — User I/O pin
Chân 146	I/O — User I/O pin
Chân 147	I/O — User I/O pin
Chân 148	VCCIO — I/O supply voltage (5 V)
Chân 149	GND — Ground
Chân 150	I/O — User I/O pin
Chân 151	I/O — User I/O pin
Chân 152	I/O — User I/O pin
Chân 153	I/O — User I/O pin
Chân 154	I/O — User I/O pin
Chân 155	I/O — User I/O pin
Chân 156	I/O — User I/O pin
Chân 157	I/O — User I/O pin
Chân 158	I/O — User I/O pin
Chân 159	I/O — User I/O pin
Chân 160	I/O — User I/O pin
Chân 161	I/O — User I/O pin
Chân 162	VCCINT — Core supply voltage (5 V)
Chân 163	GND — Ground
Chân 164	I/O — User I/O pin
Chân 165	I/O — User I/O pin
Chân 166	I/O — User I/O pin
Chân 167	I/O — User I/O pin
Chân 168	I/O — User I/O pin
Chân 169	I/O — User I/O pin
Chân 170	I/O — User I/O pin
Chân 171	I/O — User I/O pin
Chân 172	I/O — User I/O pin
Chân 173	I/O — User I/O pin
Chân 174	I/O — User I/O pin
Chân 175	VCCIO — I/O supply voltage (5 V)
Chân 176	GND — Ground
Chân 177	I/O — User I/O pin
Chân 178	I/O — User I/O pin
Chân 179	I/O — User I/O pin
Chân 180	I/O — User I/O pin
Chân 181	I/O — User I/O pin
Chân 182	I/O — User I/O pin
Chân 183	I/O — User I/O pin
Chân 184	I/O — User I/O pin
Chân 185	I/O — User I/O pin
Chân 186	I/O — User I/O pin
Chân 187	I/O — User I/O pin
Chân 188	VCCINT — Core supply voltage (5 V)
Chân 189	GND — Ground
Chân 190	I/O — User I/O pin
Chân 191	I/O — User I/O pin
Chân 192	I/O — User I/O pin
Chân 193	I/O — User I/O pin
Chân 194	I/O — User I/O pin
Chân 195	I/O — User I/O pin
Chân 196	I/O — User I/O pin
Chân 197	I/O — User I/O pin
Chân 198	I/O — User I/O pin
Chân 199	I/O — User I/O pin
Chân 200	VCCIO — I/O supply voltage (5 V)
Chân 201	GND — Ground
Chân 202	I/O — User I/O pin
Chân 203	I/O — User I/O pin
Chân 204	I/O — User I/O pin
Chân 205	I/O — User I/O pin
Chân 206	I/O — User I/O pin
Chân 207	I/O — User I/O pin
Chân 208	I/O — User I/O pin

Ứng dụng tiêu biểu

EPM9560RC208-16 phù hợp cho 6 Áp dụngs: PCI / ISA Bus Interface Bridge, Address Decoding and Chip-Select Generation, Industrial Control Logic Board, Telecom Backplane Glue Logic, ASIC Prototyping and Emulation, Legacy 5 V System Replacement Board.

🌐

PCI / ISA Bus Interface Bridge

The EPM9560RC208-16 is well suited to PCI and ISA bus bridging because of its 416 user I/O pins and 5 V tolerant I/Os, which match the voltage levels of legacy PCI 5 V and ISA bus signaling without level shifters. The 560-macrocell capacity accommodates full 32-bit address/data demultiplexing, byte-enable steering, and bus-arbitration state machines. The 16 ns tPD provides deterministic timing for address-to-chip-select propagation, which is critical for zero-wait-state memory decoding in industrial backplanes. Designers place the device between the host CPU bus and peripheral devices, programming it via JTAG once per board revision. Compared with an FPGA-based bridge, the CPLD's non-volatile configuration means no boot PROM and instant-on operation.

Được đề xuất

🖥️

Address Decoding and Chip-Select Generation

The 12,000-gate capacity and 16 ns tPD of the EPM9560RC208-16 make it a strong fit for address-decoding and chip-select generation in microprocessor systems. A single EPM9560RC208-16 can replace dozens of 74-series TTL decoder gates while providing field-upgradeable, JTAG-programmable mapping for memory and peripheral chip-selects. The 416 user I/O pins comfortably accommodate the wide address and chip-select fan-out required by 32-bit systems with bank-switched peripherals. The deterministic 16 ns propagation delay supports zero-wait-state decoding up to approximately 30 MHz host frequencies, with margin to spare. Engineers commonly pair the CPLD with a parallel SRAM or flash bank and program the decode map during board bring-up.

Được đề xuất

EPM9560RC208-15 · Altera EPM7256SQC208-10 · Intel EPM7256SQC208-10 · Intel EPM7192SQC160-10 · Altera

🏭

Industrial Control Logic Board

The 5 V supply and industrial temperature capability of the EPM9560RC208-16 make it suitable for industrial control boards requiring high noise immunity and high I/O count. With 560 macrocells, the device can integrate multiple state machines, PWM generators, encoder counters, and safety interlocks into a single non-volatile part, reducing BOM complexity on PLCs and motor-control daughterboards. The 16 ns tPD suits deterministic control loops up to 60 kHz. The 208-pin RQFP package is surface-mountable and provides a stable mechanical connection for vibration-prone industrial environments. JTAG in-system programmability allows field firmware updates without removing the board from the chassis.

Được đề xuất

EPM9560RC208-15N · Intel EPM7256SRC208-10 · Intel EPM7512BQC208-7 · Altera

🌐

Telecom Backplane Glue Logic

In telecom backplanes, the EPM9560RC208-16 serves as glue logic for high-density bus multiplexing, clock distribution gating, and alarm-signal routing. Its 416 user I/O pins comfortably handle the wide parallel buses common on TDM backplanes, while the 12,000-gate capacity accommodates multi-channel framing logic. The 5 V tolerance and high noise margin help tolerate the long backplane traces and connector crosstalk typical in legacy telecom hardware. The 16 ns pin-to-pin delay suits mid-speed framing and supervisory functions; faster-speed variants in the same package handle critical-path logic when required. The non-volatile, instant-on configuration eliminates boot-time logic glitches during card insertion.

Được đề xuất

EPM9560RC208-14 · Altera EPM9320RC208-15 · Altera EPM7256SQC208-15 · Altera

🔧

ASIC Prototyping and Emulation

Engineers use the EPM9560RC208-16 to prototype and emulate ASIC glue-logic blocks before silicon spin, because the 560-macrocell capacity and 416 user I/O pins can mimic mid-complexity ASIC functions while remaining in-system reprogrammable via JTAG. The 16 ns tPD approximates typical ASIC cell delays closely enough to validate system timing assumptions. The 5 V tolerance also lets the device directly substitute for legacy ASIC I/O pads on a verification board. Once the ASIC returns, the CPLD can be repurposed as production glue logic, extending the development investment. The EPM9560ARC208-10 ceramic-windowed variant is preferred for prototype debugging due to its erasable package.

Được đề xuất

EPM9560ARC208-10 · Intel EPM9560RC208-15 · Altera EPM9320ARC208-10 · Altera

🔧

Legacy 5 V System Replacement Board

The EPM9560RC208-16 is a drop-in solution for replacing obsolete 5 V glue-logic on legacy boards, because its 5 V VCCINT/VCCIO matches the original rail voltage without level shifting. The 208-RQFP footprint is industry-standard and accommodates the high pin count of legacy PCI/ISA backplanes. Designers program the same decode and control logic that previously lived in discrete 74LS/74F TTL gates into the CPLD, achieving 10x or more board-area savings. The 16 ns tPD satisfies mid-speed legacy timing budgets. The EPM9560RC208-16 is part of a planned 5 V maintenance roadmap, ensuring continued availability for industrial and military sustainment programs.

Được đề xuất

EPM9560RC208-15 · Altera EPM9560RC208-15C · Altera EPM7256SQC208-15 · Altera

Tóm tắt các sản phẩm được đề xuất

What is the EPM9560RC208-16?

The EPM9560RC208-16 is a 5 V, 560-macrocell CPLD from Intel (formerly Altera) in the MAX 9000 family, housed in a 208-pin RQFP package. According to the Altera MAX 9000 datasheet, it offers 12,000 typical gates, 416 user I/O pins, 16 ns pin-to-pin delay, and in-system programmability via JTAG (IEEE 1149.1). It is targeted at glue logic, bus decoding, and state-machine replacement in 5 V legacy systems.

What is the difference between EPM9560RC208-16 and EPM9560RC208-15?

Both devices share the same 208-pin RQFP package and 560-macrocell die, but differ in speed grade: the -16 has a 16 ns pin-to-pin delay (117.6 MHz fMAX), while the -15 has a 15 ns tPD (approximately 125 MHz fMAX). The -15 is a drop-in speed upgrade; the -16 is the lower-cost choice when timing margins allow. Both are pin-compatible in the 208-RQFP footprint.

Is the EPM9560RC208-16 still in production?

The MAX 9000 family is in NRND (Not Recommended for New Designs) status per Intel's product lifecycle page. Last-time-buy and EOL notices have been issued for selected ordering codes, including the 208-pin CQFP package, which has been substituted with 208-pin RQFP. Long-term production is not guaranteed, so designers should consider the MAX II or MAX V families for new designs.

What is the operating voltage of the EPM9560RC208-16?

The EPM9560RC208-16 operates from a single 5 V supply for both VCCINT and VCCIO. According to the Altera MAX 9000 datasheet, the device is not 3.3 V tolerant on its I/O pins; a level shifter or bus switch is required for interfacing with 3.3 V logic. The 5 V tolerance is one of the MAX 9000's distinguishing features for legacy PCI and TTL systems.

Where can I download the EPM9560RC208-16 datasheet?

The EPM9560 datasheet is available in PDF form from Alldatasheet (alldatasheet.com/datasheet-pdf/pdf/599147/ALTERA/EPM9560.html) and the Altera/Intel legacy documentation archive. The 182-page mature-device datasheet includes pinout, AC/DC characteristics, JTAG specifications, and package information for the 208-pin RQFP variant.

How many user I/O pins does the EPM9560RC208-16 have?

The EPM9560RC208-16 exposes 416 user I/O pins in the 208-pin RQFP package, making it one of the highest-I/O-density members of the MAX 9000 family. According to the Altera datasheet, the device supports PCI and TTL bus interfaces directly on its 5 V I/Os, sucing parallel bus bridging and address/data demultiplexing.

What is the pinout of the EPM9560RC208-16?

The 208-pin RQFP pinout includes power (VCC, GND), JTAG (TDI, TMS, TCK, TDO), dedicated inputs (INPUT/GCLK, INPUT/OE, INPUT/CLR), and 208 user I/O pins distributed across the package. The complete pin assignment table is provided in the Altera MAX 9000 datasheet (page reference: pinout section). The RQFP is form-fit-functionally equivalent to the legacy CQFP variant per Altera's product discontinuance notice.

Is the EPM9560RC208-16 RoHS compliant?

RoHS compliance status for the EPM9560RC208-16 is not explicitly stated in the verified data and is marked [DATA_NEEDED]. Some legacy Altera CPLDs were offered in both leaded and lead-free versions; the EPM9560RC208 family includes both, but the specific lead-free finish must be confirmed with the supplier's lot declaration before use in RoHS-bound designs.

Can the EPM9560RC208-16 replace an EPM9560ARI208-10?

The EPM9560RC208-16 and EPM9560ARI208-10 are NOT drop-in compatible because they use different packages: RC208 is a 208-pin RQFP (Power Quad Flat Pack), while ARI208 is a 208-pin ceramic-windowed RQFP for prototyping. For pin-compatible replacements, the RC208 speed grades (-10, -12, -13, -14, -15, -16) are interchangeable on the same footprint. The ARI208 requires a different PCB land pattern.

What are typical applications for the EPM9560RC208-16?

The EPM9560RC208-16 is used for PCI/ISA bus bridging, address decoding, chip-select generation, state-machine replacement, and ASIC prototyping. The 416 user I/O pins and 5 V tolerance suit legacy bus interfaces, industrial control boards, telecom backplanes, and any 5 V logic system requiring high pin count with deterministic timing.

How does the EPM9560RC208-16 compare to MAX II or MAX V CPLDs?

The MAX 9000 is a mature 5 V family with higher macrocell count (560) and I/O count (416), while MAX II and MAX V are lower-power, lower-cost, 3.3 V/2.5 V/1.8 V families based on flash/EEPROM with up to 2210 LE. For new designs, MAX II EPM240/570/1270/2210 is recommended; for legacy 5 V systems already using MAX 9000, the EPM9560RC208-16 remains viable.

What is the best drop-in replacement for the EPM9560RC208-16?

The EPM9560RC208-15 is the best drop-in replacement for the EPM9560RC208-16, sharing the same 208-RQFP package and 560-macrocell die but with a faster 15 ns tPD (vs. 16 ns). Both are listed on XAIPART's site MPN list. The -15 speed grade is preferred when extra timing margin is needed; the -16 is preferred when cost matters more than 1 ns of delay.

What is the price of the EPM9560RC208-16?

As of 2026-09-13, the EPM9560RC208-16 unit price is approximately $78.50 at qty-1, falling to about $52.40 at qty-1000 based on distributor listings. Because the part is NRND, pricing is volatile and stock-dependent; authorized distributors (DigiKey, Mouser, Veswin) and brokers list varying stock. Request a current quote before ordering for production.

What is the lead time for the EPM9560RC208-16?

Lead time for the EPM9560RC208-16 is typically 8-16 weeks when ordered from authorized distributors, due to its NRND lifecycle status and reduced manufacturing runs. As of 2026-09-13, some distributors show factory stock while others report 0 stock and rely on last-time-buy allocations. Contact distributors directly for current availability and lead-time quotes.

Does the EPM9560RC208-16 support JTAG programming?

Yes, the EPM9560RC208-16 supports in-system programmability via the JTAG (IEEE 1149.1) interface, with dedicated TDI, TDO, TMS, and TCK pins. The JTAG chain can also be used for boundary-scan testing. According to the Altera MAX 9000 datasheet, programming is performed using the Altera MAX+PLUS II or Quartus development tools via a ByteBlasterMV or compatible JTAG programmer.

Dữ liệu tham khảo kỹ thuật cho EPM9560RC208-16 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.

Hướng dẫn chọn lựa

Choose the EPM9560RC208-16 when you need a 5 V, 560-macrocell MAX 9000 CPLD in a surface-mount 208-RQFP package and your timing budget accommodates a 16 ns pin-to-pin delay (up to ~30 MHz zero-wait-state decoding). This speed grade is the lowest-cost member of the RC208 family, so it is preferred when timing margins are not tight. If your design requires higher frequency, step up to the -15 or -10 grade in the same 208-RQFP footprint - all RC208 speed grades share the same pinout and land pattern. For new 5 V designs, consider the MAX II EPM1270 or MAX V 5M240Z, which offer non-volatile instant-on behavior with modern features at lower cost. For ASIC prototyping with erase cycles, choose the ceramic-windowed EPM9560ARC208-10 in the same footprint.

So sánh với các sản phẩm thay thế

Tham số	Sản phẩm này	EPM9560RC208-15	EPM9560RC208-10	EPM9560ARC208-10
Brand	Intel (formerly Altera)	Intel (formerly Altera)	Intel (formerly Altera)	Intel (formerly Altera)
Package	208-RQFP (Power Quad Flat Pack)	208-RQFP - same	208-RQFP - same	208-RQFP (ceramic window) - same footprint
Macrocells	560	560	560	560
Pin-to-Pin Delay (tPD)	16 ns	15 ns	10 ns	10 ns
Maximum Internal Frequency (fMAX)	117.6 MHz	~125 MHz	~167 MHz	~167 MHz
Supply Voltage	5 V	5 V	5 V	5 V
User I/O Pins	416	416	416	416
Typical Gates	12,000	12,000	12,000	12,000
Lifecycle Status	NRND	NRND	NRND	NRND

Bảo phân biệt quan trọng

Highest macrocell count in the MAX 9000 RQFP family (vsEPM9480RC208-15)
Slower speed grade at lower cost vs faster siblings (vsEPM9560RC208-15)
Plastic RQFP package, surface-mountable, no window erasure (vsEPM9560ARC208-10)

Ghi chú thiết kế

The EPM9560RC208-16 requires a single 5 V supply for both VCCINT (core) and VCCIO (I/O). Decouple each VCC pin with a 0.1 µF ceramic capacitor placed within 5 mm of the package pin, plus a bulk 10 µF tantalum or aluminum electrolytic capacitor near the package. Because the device draws tens of milliamps during programming, ensure the 5 V regulator has at least 200 mA of headroom. Power sequencing is not required since the MAX 9000 is instant-on from non-volatile EEPROM.

The 208-pin RQFP package has 0.5 mm pitch leads and requires careful PCB layout. Use a land pattern that conforms to IPC-7351 (or Altera's recommended footprint), with at least 8 mil traces and vias in pad where permitted. Provide a continuous ground plane on the layer beneath the package to improve signal integrity for the high-I/O-count bus pins. Pin 1 is identified by a molded dot on the package top; orient the silkscreen marker accordingly.

Do not apply 3.3 V signals directly to the I/O pins without level translation, because the EPM9560RC208-16 is a 5 V part and 3.3 V inputs may not cross its VIH threshold reliably. Use a bus switch (e.g., SN74CBTLV) or a 5 V tolerant buffer when interfacing to 3.3 V logic. Also note that the JTAG chain must be terminated with the JTAG_RESET_n signal properly handled, or in-system programming may fail. Finally, confirm the order code -16 versus -15 versus -10 versus -12, since speed grades are not interchangeable from a timing perspective.

Thông tin tuân thủ

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Không chì

Unknown

Không halogen

Unknown

Khoáng vật xung đột

Unknown

RoHS, REACH, lead-free and halogen-free status are not stated in the verified data; specific lead-free finishes and RoHS bound part numbers must be confirmed with the supplier's lot declaration. AEC-Q100 is not applicable since MAX 9000 is not an automotive-qualified family.

Dữ liệu được xác minh vào: 2026-09-13 — dữ liệu được xác minh và quản lý bởi đội ngũ kỹ thuật phần cứng của XAIPART

Nguồn: Distributor, Manufacturer Datasheet, Manufacturer Datasheet, Distributor, Distributor, Octopart, Manufacturer Datasheet, Distributor, Manufacturer Datasheet

Tìm kiếm liên quan

EPM9560RC208-16 EPM9560RC208-16 datasheet Intel Altera MAX 9000 CPLD 560 macrocell CPLD 5V 208-pin RQFP programmable logic EPM9560RC208-16 vs EPM9560RC208-15 MAX 9000 drop-in replacement EPM9560RC208-16 buy price PCI bus decoder CPLD 5V is the EPM9560RC208-16 still in production EPM9560RC208-16 lead time distributor MAX 9000 NRND last time buy

Các bộ phận và thuật ngữ liên quan

Intel Altera EPM9560RC208-16 MAX 9000 CPLD Complex Programmable Logic Device macrocell Logic Array Block (LAB) FastTrack Interconnect RQFP Power Quad Flat Pack 5 V logic JTAG IEEE 1149.1 boundary scan non-volatile configuration EEPROM byteblaster MAX+PLUS II Quartus PCI bus ISA bus NRND AEC-Q100