EP1810LC-25 vs EP1810LC-35T 比較
詳細並排比較 EP1810LC-25 由 Altera 與 EP1810LC-35T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810LC-25 | EP1810LC-35T |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| 封裝 | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Code | LC = 68-pin JLCC | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| 生命週期狀態 | Obsolete (legacy Altera Classic family) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | Non-compliant (legacy PLCC product) |
| 工作溫度 | [DATA_NEEDED: temperature grade for LC package] | 0 C to +70 C (Commercial) |
| Device Family | — | EP1810 Classic EPLD |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Logic Compatibility | — | 100% TTL emulation |
| Package Suffix | — | T = Tape and Reel |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |